mirror of https://gitlab.freedesktop.org/mesa/mesa
476 lines
14 KiB
C
476 lines
14 KiB
C
/*
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* Copyright © 2021 Ilia Mirkin
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <limits.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <sys/ioctl.h>
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#include "drm-uapi/nouveau_drm.h"
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#include "nouveau/nvif/ioctl.h"
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#include "nouveau/nvif/cl0080.h"
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#include "drm-shim/drm_shim.h"
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#include "util//u_math.h"
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#include "../../gallium/drivers/nouveau/nv_object.xml.h"
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bool drm_shim_driver_prefers_first_render_node = true;
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struct nouveau_device {
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uint64_t next_offset;
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};
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static struct nouveau_device nouveau = {
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.next_offset = 0x1000,
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};
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struct nouveau_shim_bo {
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struct shim_bo base;
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uint64_t offset;
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};
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static struct nouveau_shim_bo *
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nouveau_shim_bo(struct shim_bo *bo)
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{
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return (struct nouveau_shim_bo *)bo;
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}
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struct nouveau_device_info {
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uint32_t chip_id;
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};
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static struct nouveau_device_info device_info;
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static int
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nouveau_ioctl_noop(int fd, unsigned long request, void *arg)
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{
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return 0;
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}
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static int
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nouveau_ioctl_gem_new(int fd, unsigned long request, void *arg)
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{
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_nouveau_gem_new *create = arg;
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struct nouveau_shim_bo *bo = calloc(1, sizeof(*bo));
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drm_shim_bo_init(&bo->base, create->info.size);
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assert(ULONG_MAX - nouveau.next_offset > create->info.size);
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create->info.handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
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create->info.map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
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if (create->align != 0)
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nouveau.next_offset = align64(nouveau.next_offset, create->align);
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create->info.offset = nouveau.next_offset;
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nouveau.next_offset += create->info.size;
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bo->offset = create->info.offset;
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drm_shim_bo_put(&bo->base);
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return 0;
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}
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static int
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nouveau_ioctl_gem_info(int fd, unsigned long request, void *arg)
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{
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_nouveau_gem_info *info = arg;
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struct nouveau_shim_bo *bo =
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nouveau_shim_bo(drm_shim_bo_lookup(shim_fd, info->handle));
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info->map_handle = drm_shim_bo_get_mmap_offset(shim_fd, &bo->base);
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info->offset = bo->offset;
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info->size = bo->base.size;
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drm_shim_bo_put(&bo->base);
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return 0;
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}
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static int
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nouveau_ioctl_gem_pushbuf(int fd, unsigned long request, void *arg)
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{
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struct drm_nouveau_gem_pushbuf *submit = arg;
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submit->vram_available = 3ULL << 30;
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submit->gart_available = 1ULL << 40;
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return 0;
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}
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static int
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nouveau_ioctl_channel_alloc(int fd, unsigned long request, void *arg)
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{
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struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
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struct drm_nouveau_channel_alloc *alloc = arg;
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if (device_info.chip_id == 0x50 || device_info.chip_id >= 0x80)
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alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART;
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else
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alloc->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
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/* NOTE: this will get leaked since we don't handle the channel
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* free. However only one channel is created per screen, so impact should
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* be limited. */
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struct nouveau_shim_bo *notify = calloc(1, sizeof(*notify));
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drm_shim_bo_init(¬ify->base, 0x1000);
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notify->offset = nouveau.next_offset;
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nouveau.next_offset += 0x1000;
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alloc->notifier_handle = drm_shim_bo_get_handle(shim_fd, ¬ify->base);
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drm_shim_bo_put(¬ify->base);
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return 0;
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}
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static int
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nouveau_ioctl_get_param(int fd, unsigned long request, void *arg)
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{
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struct drm_nouveau_getparam *gp = arg;
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switch (gp->param) {
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case NOUVEAU_GETPARAM_CHIPSET_ID:
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gp->value = device_info.chip_id;
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return 0;
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case NOUVEAU_GETPARAM_PCI_VENDOR:
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gp->value = 0x10de;
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return 0;
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case NOUVEAU_GETPARAM_PCI_DEVICE:
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gp->value = 0x1004;
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return 0;
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case NOUVEAU_GETPARAM_BUS_TYPE:
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gp->value = 2 /* NV_PCIE */;
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return 0;
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case NOUVEAU_GETPARAM_FB_SIZE:
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gp->value = 3ULL << 30;
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return 0;
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case NOUVEAU_GETPARAM_AGP_SIZE:
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gp->value = 1ULL << 40;
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return 0;
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case NOUVEAU_GETPARAM_PTIMER_TIME:
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gp->value = 0;
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return 0;
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case NOUVEAU_GETPARAM_HAS_BO_USAGE:
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gp->value = 1;
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return 0;
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case NOUVEAU_GETPARAM_GRAPH_UNITS:
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gp->value = 0x01000101;
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return 0;
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default:
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fprintf(stderr, "Unknown DRM_IOCTL_NOUVEAU_GETPARAM %llu\n",
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(long long unsigned)gp->param);
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return -1;
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}
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}
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static int
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nouveau_ioctl_nvif(int fd, unsigned long request, void *arg)
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{
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struct {
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struct nvif_ioctl_v0 ioctl;
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} *args = arg;
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switch (args->ioctl.type) {
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case NVIF_IOCTL_V0_MTHD: {
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struct {
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struct nvif_ioctl_v0 ioctl;
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struct nvif_ioctl_mthd_v0 mthd;
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} *mthd = (void *)args;
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switch (mthd->mthd.method) {
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case NV_DEVICE_V0_INFO: {
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struct nv_device_info_v0 *info = (void *)&mthd->mthd.data;
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info->chipset = device_info.chip_id;
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info->platform = NV_DEVICE_INFO_V0_PCIE;
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break;
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}
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default:
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break;
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}
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break;
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}
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case NVIF_IOCTL_V0_SCLASS: {
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struct {
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struct nvif_ioctl_v0 ioctl;
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struct nvif_ioctl_sclass_v0 sclass;
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} *sclass = (void *)args;
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if (sclass->sclass.count == 0) {
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sclass->sclass.count = device_info.chip_id >= 0xe0 ? 4 : 3;
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return 0;
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}
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int idx = 0;
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/* m2mf */
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switch (device_info.chip_id & ~0xf) {
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case 0x170:
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case 0x160:
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case 0x140:
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case 0x130:
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case 0x120:
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case 0x110:
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case 0x100:
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case 0xf0:
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sclass->sclass.oclass[idx].oclass = NVF0_P2MF_CLASS;
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break;
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case 0xe0:
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sclass->sclass.oclass[idx].oclass = NVE4_P2MF_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = NVC0_M2MF_CLASS;
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break;
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}
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sclass->sclass.oclass[idx].minver = -1;
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sclass->sclass.oclass[idx].maxver = -1;
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idx++;
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if (device_info.chip_id >= 0xe0) {
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switch (device_info.chip_id & ~0xf) {
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case 0x170:
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sclass->sclass.oclass[idx].oclass = AMPERE_DMA_COPY_A;
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break;
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case 0x160:
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sclass->sclass.oclass[idx].oclass = TURING_DMA_COPY_A;
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break;
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case 0x140:
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sclass->sclass.oclass[idx].oclass = VOLTA_DMA_COPY_A;
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break;
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case 0x130:
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sclass->sclass.oclass[idx].oclass = PASCAL_DMA_COPY_A;
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break;
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case 0x120:
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case 0x110:
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sclass->sclass.oclass[idx].oclass = MAXWELL_DMA_COPY_A;
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break;
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case 0x100:
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case 0xf0:
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case 0xe0:
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sclass->sclass.oclass[idx].oclass = KEPLER_DMA_COPY_A;
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break;
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}
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sclass->sclass.oclass[idx].minver = -1;
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sclass->sclass.oclass[idx].maxver = -1;
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idx++;
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}
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/* 2d */
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if (device_info.chip_id >= 0x50) {
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if (device_info.chip_id <= 0xa0)
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sclass->sclass.oclass[idx].oclass = NV50_2D_CLASS;
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else
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sclass->sclass.oclass[idx].oclass = NVC0_2D_CLASS;
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sclass->sclass.oclass[idx].minver = -1;
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sclass->sclass.oclass[idx].maxver = -1;
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idx++;
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}
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/* 3d */
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switch (device_info.chip_id & ~0xf) {
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case 0x170:
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sclass->sclass.oclass[idx].oclass = GA102_3D_CLASS;
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break;
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case 0x160:
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sclass->sclass.oclass[idx].oclass = TU102_3D_CLASS;
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break;
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case 0x140:
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sclass->sclass.oclass[idx].oclass = GV100_3D_CLASS;
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break;
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case 0x130:
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switch (device_info.chip_id) {
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case 0x130:
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case 0x13b:
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sclass->sclass.oclass[idx].oclass = GP100_3D_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = GP102_3D_CLASS;
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break;
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}
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break;
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case 0x120:
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sclass->sclass.oclass[idx].oclass = GM200_3D_CLASS;
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break;
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case 0x110:
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sclass->sclass.oclass[idx].oclass = GM107_3D_CLASS;
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break;
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case 0x100:
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case 0xf0:
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sclass->sclass.oclass[idx].oclass = NVF0_3D_CLASS;
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break;
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case 0xe0:
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switch (device_info.chip_id) {
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case 0xea:
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sclass->sclass.oclass[idx].oclass = NVEA_3D_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = NVE4_3D_CLASS;
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break;
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}
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break;
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case 0xd0:
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sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
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break;
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default:
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case 0xc0:
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switch (device_info.chip_id) {
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case 0xc8:
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sclass->sclass.oclass[idx].oclass = NVC8_3D_CLASS;
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break;
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case 0xc1:
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sclass->sclass.oclass[idx].oclass = NVC1_3D_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = NVC0_3D_CLASS;
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break;
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}
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break;
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}
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sclass->sclass.oclass[idx].minver = -1;
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sclass->sclass.oclass[idx].maxver = -1;
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idx++;
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switch (device_info.chip_id & ~0xf) {
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case 0x170:
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sclass->sclass.oclass[idx].oclass = GA102_COMPUTE_CLASS;
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break;
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case 0x160:
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sclass->sclass.oclass[idx].oclass = TU102_COMPUTE_CLASS;
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break;
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case 0x140:
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sclass->sclass.oclass[idx].oclass = GV100_COMPUTE_CLASS;
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break;
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case 0x130:
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switch (device_info.chip_id) {
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case 0x130:
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case 0x13b:
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sclass->sclass.oclass[idx].oclass = GP100_COMPUTE_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = GP104_COMPUTE_CLASS;
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break;
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}
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break;
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case 0x120:
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sclass->sclass.oclass[idx].oclass = GM200_COMPUTE_CLASS;
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break;
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case 0x110:
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sclass->sclass.oclass[idx].oclass = GM107_COMPUTE_CLASS;
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break;
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case 0x100:
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case 0xf0:
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sclass->sclass.oclass[idx].oclass = NVF0_COMPUTE_CLASS;
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break;
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case 0xe0:
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sclass->sclass.oclass[idx].oclass = NVE4_COMPUTE_CLASS;
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break;
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default:
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sclass->sclass.oclass[idx].oclass = NVC0_COMPUTE_CLASS;
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break;
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}
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sclass->sclass.oclass[idx].minver = -1;
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sclass->sclass.oclass[idx].maxver = -1;
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break;
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}
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default:
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break;
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}
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return 0;
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}
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static ioctl_fn_t driver_ioctls[] = {
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[DRM_NOUVEAU_GETPARAM] = nouveau_ioctl_get_param,
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[DRM_NOUVEAU_NVIF] = nouveau_ioctl_nvif,
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[DRM_NOUVEAU_CHANNEL_ALLOC] = nouveau_ioctl_channel_alloc,
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[DRM_NOUVEAU_CHANNEL_FREE] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_GROBJ_ALLOC] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_NOTIFIEROBJ_ALLOC] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_GPUOBJ_FREE] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_GEM_NEW] = nouveau_ioctl_gem_new,
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[DRM_NOUVEAU_GEM_PUSHBUF] = nouveau_ioctl_gem_pushbuf,
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[DRM_NOUVEAU_GEM_CPU_PREP] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_GEM_INFO] = nouveau_ioctl_gem_info,
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[DRM_NOUVEAU_GEM_CPU_FINI] = nouveau_ioctl_gem_info,
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[DRM_NOUVEAU_VM_INIT] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_VM_BIND] = nouveau_ioctl_noop,
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[DRM_NOUVEAU_EXEC] = nouveau_ioctl_noop,
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};
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static void
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nouveau_driver_get_device_info(void)
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{
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const char *env = getenv("NOUVEAU_CHIPSET");
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if (!env) {
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device_info.chip_id = 0xf0;
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return;
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}
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device_info.chip_id = strtol(env, NULL, 16);
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}
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void
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drm_shim_driver_init(void)
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{
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shim_device.bus_type = DRM_BUS_PCI;
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shim_device.driver_name = "nouveau";
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shim_device.driver_ioctls = driver_ioctls;
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shim_device.driver_ioctl_count = ARRAY_SIZE(driver_ioctls);
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shim_device.version_major = 1;
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shim_device.version_minor = 3;
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shim_device.version_patchlevel = 1;
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nouveau_driver_get_device_info();
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/* Ask userspace to consider all fences completed. */
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setenv("NOUVEAU_DISABLE_FENCES", "true", true);
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/* nothing looks at the pci id, so fix it to a GTX 780 */
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static const char uevent_content[] =
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"DRIVER=nouveau\n"
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"PCI_CLASS=30000\n"
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"PCI_ID=10de:1004\n"
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"PCI_SUBSYS_ID=1028:075B\n"
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"PCI_SLOT_NAME=0000:01:00.0\n"
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"MODALIAS=pci:v000010ded00005916sv00001028sd0000075Bbc03sc00i00\n";
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drm_shim_override_file(uevent_content,
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"/sys/dev/char/%d:%d/device/uevent",
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DRM_MAJOR, render_node_minor);
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drm_shim_override_file("0x0\n",
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"/sys/dev/char/%d:%d/device/revision",
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DRM_MAJOR, render_node_minor);
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drm_shim_override_file("0x10de",
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"/sys/dev/char/%d:%d/device/vendor",
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DRM_MAJOR, render_node_minor);
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drm_shim_override_file("0x10de",
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"/sys/devices/pci0000:00/0000:01:00.0/vendor");
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drm_shim_override_file("0x1004",
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"/sys/dev/char/%d:%d/device/device",
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DRM_MAJOR, render_node_minor);
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drm_shim_override_file("0x1004",
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"/sys/devices/pci0000:00/0000:01:00.0/device");
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drm_shim_override_file("0x1234",
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"/sys/dev/char/%d:%d/device/subsystem_vendor",
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DRM_MAJOR, render_node_minor);
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drm_shim_override_file("0x1234",
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"/sys/devices/pci0000:00/0000:01:00.0/subsystem_vendor");
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drm_shim_override_file("0x1234",
|
|
"/sys/dev/char/%d:%d/device/subsystem_device",
|
|
DRM_MAJOR, render_node_minor);
|
|
drm_shim_override_file("0x1234",
|
|
"/sys/devices/pci0000:00/0000:01:00.0/subsystem_device");
|
|
}
|