mirror of https://gitlab.freedesktop.org/mesa/mesa
735 lines
19 KiB
C++
735 lines
19 KiB
C++
/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_cfg.h"
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#include "brw_eu.h"
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#include "brw_fs.h"
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#include "brw_nir.h"
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#include "brw_private.h"
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#include "dev/intel_debug.h"
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#include "util/macros.h"
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bool
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fs_reg_saturate_immediate(fs_reg *reg)
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{
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union {
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unsigned ud;
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int d;
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float f;
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double df;
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} imm, sat_imm = { 0 };
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const unsigned size = brw_type_size_bytes(reg->type);
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/* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
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* irrelevant, so just check the size of the type and copy from/to an
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* appropriately sized field.
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*/
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if (size < 8)
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imm.ud = reg->ud;
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else
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imm.df = reg->df;
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switch (reg->type) {
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case BRW_TYPE_UD:
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case BRW_TYPE_D:
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case BRW_TYPE_UW:
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case BRW_TYPE_W:
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case BRW_TYPE_UQ:
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case BRW_TYPE_Q:
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/* Nothing to do. */
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return false;
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case BRW_TYPE_F:
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sat_imm.f = SATURATE(imm.f);
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break;
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case BRW_TYPE_DF:
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sat_imm.df = SATURATE(imm.df);
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break;
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case BRW_TYPE_UB:
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case BRW_TYPE_B:
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unreachable("no UB/B immediates");
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case BRW_TYPE_V:
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case BRW_TYPE_UV:
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case BRW_TYPE_VF:
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unreachable("unimplemented: saturate vector immediate");
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case BRW_TYPE_HF:
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unreachable("unimplemented: saturate HF immediate");
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default:
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unreachable("invalid type");
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}
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if (size < 8) {
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if (imm.ud != sat_imm.ud) {
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reg->ud = sat_imm.ud;
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return true;
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}
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} else {
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if (imm.df != sat_imm.df) {
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reg->df = sat_imm.df;
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return true;
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}
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}
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return false;
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}
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bool
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fs_reg_negate_immediate(fs_reg *reg)
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{
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switch (reg->type) {
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case BRW_TYPE_D:
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case BRW_TYPE_UD:
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reg->d = -reg->d;
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return true;
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case BRW_TYPE_W:
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case BRW_TYPE_UW: {
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uint16_t value = -(int16_t)reg->ud;
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reg->ud = value | (uint32_t)value << 16;
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return true;
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}
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case BRW_TYPE_F:
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reg->f = -reg->f;
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return true;
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case BRW_TYPE_VF:
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reg->ud ^= 0x80808080;
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return true;
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case BRW_TYPE_DF:
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reg->df = -reg->df;
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return true;
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case BRW_TYPE_UQ:
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case BRW_TYPE_Q:
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reg->d64 = -reg->d64;
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return true;
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case BRW_TYPE_UB:
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case BRW_TYPE_B:
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unreachable("no UB/B immediates");
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case BRW_TYPE_UV:
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case BRW_TYPE_V:
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assert(!"unimplemented: negate UV/V immediate");
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case BRW_TYPE_HF:
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reg->ud ^= 0x80008000;
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return true;
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default:
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unreachable("invalid type");
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}
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return false;
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}
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bool
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fs_reg_abs_immediate(fs_reg *reg)
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{
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switch (reg->type) {
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case BRW_TYPE_D:
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reg->d = abs(reg->d);
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return true;
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case BRW_TYPE_W: {
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uint16_t value = abs((int16_t)reg->ud);
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reg->ud = value | (uint32_t)value << 16;
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return true;
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}
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case BRW_TYPE_F:
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reg->f = fabsf(reg->f);
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return true;
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case BRW_TYPE_DF:
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reg->df = fabs(reg->df);
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return true;
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case BRW_TYPE_VF:
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reg->ud &= ~0x80808080;
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return true;
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case BRW_TYPE_Q:
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reg->d64 = imaxabs(reg->d64);
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return true;
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case BRW_TYPE_UB:
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case BRW_TYPE_B:
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unreachable("no UB/B immediates");
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case BRW_TYPE_UQ:
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case BRW_TYPE_UD:
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case BRW_TYPE_UW:
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case BRW_TYPE_UV:
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/* Presumably the absolute value modifier on an unsigned source is a
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* nop, but it would be nice to confirm.
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*/
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assert(!"unimplemented: abs unsigned immediate");
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case BRW_TYPE_V:
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assert(!"unimplemented: abs V immediate");
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case BRW_TYPE_HF:
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reg->ud &= ~0x80008000;
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return true;
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default:
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unreachable("invalid type");
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}
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return false;
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}
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bool
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fs_reg::is_zero() const
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{
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if (file != IMM)
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return false;
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assert(brw_type_size_bytes(type) > 1);
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switch (type) {
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case BRW_TYPE_HF:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
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case BRW_TYPE_F:
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return f == 0;
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case BRW_TYPE_DF:
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return df == 0;
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case BRW_TYPE_W:
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case BRW_TYPE_UW:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 0;
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case BRW_TYPE_D:
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case BRW_TYPE_UD:
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return d == 0;
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case BRW_TYPE_UQ:
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case BRW_TYPE_Q:
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return u64 == 0;
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default:
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return false;
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}
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}
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bool
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fs_reg::is_one() const
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{
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if (file != IMM)
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return false;
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assert(brw_type_size_bytes(type) > 1);
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switch (type) {
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case BRW_TYPE_HF:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 0x3c00;
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case BRW_TYPE_F:
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return f == 1.0f;
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case BRW_TYPE_DF:
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return df == 1.0;
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case BRW_TYPE_W:
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case BRW_TYPE_UW:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 1;
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case BRW_TYPE_D:
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case BRW_TYPE_UD:
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return d == 1;
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case BRW_TYPE_UQ:
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case BRW_TYPE_Q:
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return u64 == 1;
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default:
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return false;
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}
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}
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bool
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fs_reg::is_negative_one() const
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{
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if (file != IMM)
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return false;
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assert(brw_type_size_bytes(type) > 1);
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switch (type) {
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case BRW_TYPE_HF:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 0xbc00;
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case BRW_TYPE_F:
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return f == -1.0;
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case BRW_TYPE_DF:
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return df == -1.0;
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case BRW_TYPE_W:
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assert((d & 0xffff) == ((d >> 16) & 0xffff));
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return (d & 0xffff) == 0xffff;
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case BRW_TYPE_D:
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return d == -1;
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case BRW_TYPE_Q:
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return d64 == -1;
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default:
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return false;
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}
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}
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bool
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fs_reg::is_null() const
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{
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return file == ARF && nr == BRW_ARF_NULL;
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}
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bool
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fs_reg::is_accumulator() const
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{
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return file == ARF && (nr & 0xF0) == BRW_ARF_ACCUMULATOR;
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}
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bool
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fs_inst::is_commutative() const
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{
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switch (opcode) {
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case BRW_OPCODE_AND:
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case BRW_OPCODE_OR:
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case BRW_OPCODE_XOR:
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_ADD3:
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case SHADER_OPCODE_MULH:
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return true;
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case BRW_OPCODE_MUL:
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/* Integer multiplication of dword and word sources is not actually
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* commutative. The DW source must be first.
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*/
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return !brw_type_is_int(src[0].type) ||
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brw_type_size_bits(src[0].type) == brw_type_size_bits(src[1].type);
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case BRW_OPCODE_SEL:
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/* MIN and MAX are commutative. */
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if (conditional_mod == BRW_CONDITIONAL_GE ||
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conditional_mod == BRW_CONDITIONAL_L) {
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return true;
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}
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FALLTHROUGH;
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default:
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return false;
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}
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}
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bool
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fs_inst::is_3src(const struct brw_compiler *compiler) const
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{
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return ::is_3src(&compiler->isa, opcode);
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}
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bool
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fs_inst::is_math() const
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{
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return (opcode == SHADER_OPCODE_RCP ||
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opcode == SHADER_OPCODE_RSQ ||
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opcode == SHADER_OPCODE_SQRT ||
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opcode == SHADER_OPCODE_EXP2 ||
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opcode == SHADER_OPCODE_LOG2 ||
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opcode == SHADER_OPCODE_SIN ||
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opcode == SHADER_OPCODE_COS ||
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opcode == SHADER_OPCODE_INT_QUOTIENT ||
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opcode == SHADER_OPCODE_INT_REMAINDER ||
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opcode == SHADER_OPCODE_POW);
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}
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bool
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fs_inst::is_control_flow_begin() const
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{
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switch (opcode) {
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case BRW_OPCODE_DO:
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case BRW_OPCODE_IF:
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case BRW_OPCODE_ELSE:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::is_control_flow_end() const
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{
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switch (opcode) {
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case BRW_OPCODE_ELSE:
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case BRW_OPCODE_WHILE:
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case BRW_OPCODE_ENDIF:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::is_control_flow() const
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{
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switch (opcode) {
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case BRW_OPCODE_DO:
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case BRW_OPCODE_WHILE:
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case BRW_OPCODE_IF:
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case BRW_OPCODE_ELSE:
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case BRW_OPCODE_ENDIF:
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case BRW_OPCODE_BREAK:
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case BRW_OPCODE_CONTINUE:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::uses_indirect_addressing() const
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{
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switch (opcode) {
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case SHADER_OPCODE_BROADCAST:
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case SHADER_OPCODE_CLUSTER_BROADCAST:
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case SHADER_OPCODE_MOV_INDIRECT:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::can_do_saturate() const
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{
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switch (opcode) {
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case BRW_OPCODE_ADD:
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case BRW_OPCODE_ADD3:
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case BRW_OPCODE_ASR:
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case BRW_OPCODE_AVG:
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case BRW_OPCODE_CSEL:
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case BRW_OPCODE_DP2:
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case BRW_OPCODE_DP3:
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case BRW_OPCODE_DP4:
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case BRW_OPCODE_DPH:
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case BRW_OPCODE_DP4A:
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case BRW_OPCODE_LINE:
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case BRW_OPCODE_LRP:
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case BRW_OPCODE_MAC:
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case BRW_OPCODE_MAD:
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case BRW_OPCODE_MATH:
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case BRW_OPCODE_MOV:
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case BRW_OPCODE_MUL:
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case SHADER_OPCODE_MULH:
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case BRW_OPCODE_PLN:
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case BRW_OPCODE_RNDD:
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case BRW_OPCODE_RNDE:
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case BRW_OPCODE_RNDU:
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case BRW_OPCODE_RNDZ:
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case BRW_OPCODE_SEL:
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case BRW_OPCODE_SHL:
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case BRW_OPCODE_SHR:
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case SHADER_OPCODE_COS:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_POW:
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_SQRT:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::reads_accumulator_implicitly() const
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{
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switch (opcode) {
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case BRW_OPCODE_MAC:
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case BRW_OPCODE_MACH:
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case BRW_OPCODE_SADA2:
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return true;
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default:
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return false;
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}
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}
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bool
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fs_inst::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const
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{
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return writes_accumulator ||
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(eot && intel_needs_workaround(devinfo, 14010017096));
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}
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bool
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fs_inst::has_side_effects() const
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{
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switch (opcode) {
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case SHADER_OPCODE_SEND:
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return send_has_side_effects;
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case BRW_OPCODE_SYNC:
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case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
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case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
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case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
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case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
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case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
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case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
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case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
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case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
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case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
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case SHADER_OPCODE_MEMORY_FENCE:
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case SHADER_OPCODE_INTERLOCK:
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case SHADER_OPCODE_URB_WRITE_LOGICAL:
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case FS_OPCODE_FB_WRITE_LOGICAL:
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case SHADER_OPCODE_BARRIER:
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case SHADER_OPCODE_RND_MODE:
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case SHADER_OPCODE_FLOAT_CONTROL_MODE:
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case FS_OPCODE_SCHEDULING_FENCE:
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case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
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case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
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case SHADER_OPCODE_BTD_SPAWN_LOGICAL:
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case SHADER_OPCODE_BTD_RETIRE_LOGICAL:
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case RT_OPCODE_TRACE_RAY_LOGICAL:
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return true;
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default:
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return eot;
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}
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}
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bool
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fs_inst::is_volatile() const
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{
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switch (opcode) {
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case SHADER_OPCODE_SEND:
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return send_is_volatile;
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case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
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case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
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case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
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case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
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case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
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case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
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return true;
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default:
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return false;
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}
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}
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#ifndef NDEBUG
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static bool
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inst_is_in_block(const bblock_t *block, const fs_inst *inst)
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{
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const exec_node *n = inst;
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/* Find the tail sentinel. If the tail sentinel is the sentinel from the
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* list header in the bblock_t, then this instruction is in that basic
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* block.
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*/
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while (!n->is_tail_sentinel())
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n = n->get_next();
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return n == &block->instructions.tail_sentinel;
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}
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#endif
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static void
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adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
|
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{
|
|
for (bblock_t *block_iter = start_block->next();
|
|
block_iter;
|
|
block_iter = block_iter->next()) {
|
|
block_iter->start_ip += ip_adjustment;
|
|
block_iter->end_ip += ip_adjustment;
|
|
}
|
|
}
|
|
|
|
void
|
|
fs_inst::insert_after(bblock_t *block, fs_inst *inst)
|
|
{
|
|
assert(this != inst);
|
|
assert(block->end_ip_delta == 0);
|
|
|
|
if (!this->is_head_sentinel())
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
block->end_ip++;
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
exec_node::insert_after(inst);
|
|
}
|
|
|
|
void
|
|
fs_inst::insert_before(bblock_t *block, fs_inst *inst)
|
|
{
|
|
assert(this != inst);
|
|
assert(block->end_ip_delta == 0);
|
|
|
|
if (!this->is_tail_sentinel())
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
block->end_ip++;
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
exec_node::insert_before(inst);
|
|
}
|
|
|
|
void
|
|
fs_inst::remove(bblock_t *block, bool defer_later_block_ip_updates)
|
|
{
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
if (exec_list_is_singular(&block->instructions)) {
|
|
this->opcode = BRW_OPCODE_NOP;
|
|
this->resize_sources(0);
|
|
this->dst = fs_reg();
|
|
this->size_written = 0;
|
|
return;
|
|
}
|
|
|
|
if (defer_later_block_ip_updates) {
|
|
block->end_ip_delta--;
|
|
} else {
|
|
assert(block->end_ip_delta == 0);
|
|
adjust_later_block_ips(block, -1);
|
|
}
|
|
|
|
if (block->start_ip == block->end_ip) {
|
|
if (block->end_ip_delta != 0) {
|
|
adjust_later_block_ips(block, block->end_ip_delta);
|
|
block->end_ip_delta = 0;
|
|
}
|
|
|
|
block->cfg->remove_block(block);
|
|
} else {
|
|
block->end_ip--;
|
|
}
|
|
|
|
exec_node::remove();
|
|
}
|
|
|
|
extern "C" const unsigned *
|
|
brw_compile_tes(const struct brw_compiler *compiler,
|
|
brw_compile_tes_params *params)
|
|
{
|
|
const struct intel_device_info *devinfo = compiler->devinfo;
|
|
nir_shader *nir = params->base.nir;
|
|
const struct brw_tes_prog_key *key = params->key;
|
|
const struct intel_vue_map *input_vue_map = params->input_vue_map;
|
|
struct brw_tes_prog_data *prog_data = params->prog_data;
|
|
|
|
const bool debug_enabled = brw_should_print_shader(nir, DEBUG_TES);
|
|
|
|
prog_data->base.base.stage = MESA_SHADER_TESS_EVAL;
|
|
prog_data->base.base.ray_queries = nir->info.ray_queries;
|
|
|
|
nir->info.inputs_read = key->inputs_read;
|
|
nir->info.patch_inputs_read = key->patch_inputs_read;
|
|
|
|
brw_nir_apply_key(nir, compiler, &key->base,
|
|
brw_geometry_stage_dispatch_width(compiler->devinfo));
|
|
brw_nir_lower_tes_inputs(nir, input_vue_map);
|
|
brw_nir_lower_vue_outputs(nir);
|
|
brw_postprocess_nir(nir, compiler, debug_enabled,
|
|
key->base.robust_flags);
|
|
|
|
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
|
|
nir->info.outputs_written,
|
|
nir->info.separate_shader, 1);
|
|
|
|
unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
|
|
|
|
assert(output_size_bytes >= 1);
|
|
if (output_size_bytes > GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
|
|
params->base.error_str = ralloc_strdup(params->base.mem_ctx,
|
|
"DS outputs exceed maximum size");
|
|
return NULL;
|
|
}
|
|
|
|
prog_data->base.clip_distance_mask =
|
|
((1 << nir->info.clip_distance_array_size) - 1);
|
|
prog_data->base.cull_distance_mask =
|
|
((1 << nir->info.cull_distance_array_size) - 1) <<
|
|
nir->info.clip_distance_array_size;
|
|
|
|
prog_data->include_primitive_id =
|
|
BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
|
|
|
|
/* URB entry sizes are stored as a multiple of 64 bytes. */
|
|
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
|
|
|
|
prog_data->base.urb_read_length = 0;
|
|
|
|
STATIC_ASSERT(INTEL_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
|
|
STATIC_ASSERT(INTEL_TESS_PARTITIONING_ODD_FRACTIONAL ==
|
|
TESS_SPACING_FRACTIONAL_ODD - 1);
|
|
STATIC_ASSERT(INTEL_TESS_PARTITIONING_EVEN_FRACTIONAL ==
|
|
TESS_SPACING_FRACTIONAL_EVEN - 1);
|
|
|
|
prog_data->partitioning =
|
|
(enum intel_tess_partitioning) (nir->info.tess.spacing - 1);
|
|
|
|
switch (nir->info.tess._primitive_mode) {
|
|
case TESS_PRIMITIVE_QUADS:
|
|
prog_data->domain = INTEL_TESS_DOMAIN_QUAD;
|
|
break;
|
|
case TESS_PRIMITIVE_TRIANGLES:
|
|
prog_data->domain = INTEL_TESS_DOMAIN_TRI;
|
|
break;
|
|
case TESS_PRIMITIVE_ISOLINES:
|
|
prog_data->domain = INTEL_TESS_DOMAIN_ISOLINE;
|
|
break;
|
|
default:
|
|
unreachable("invalid domain shader primitive mode");
|
|
}
|
|
|
|
if (nir->info.tess.point_mode) {
|
|
prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_POINT;
|
|
} else if (nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES) {
|
|
prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_LINE;
|
|
} else {
|
|
/* Hardware winding order is backwards from OpenGL */
|
|
prog_data->output_topology =
|
|
nir->info.tess.ccw ? INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW
|
|
: INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
|
|
}
|
|
|
|
if (unlikely(debug_enabled)) {
|
|
fprintf(stderr, "TES Input ");
|
|
brw_print_vue_map(stderr, input_vue_map, MESA_SHADER_TESS_EVAL);
|
|
fprintf(stderr, "TES Output ");
|
|
brw_print_vue_map(stderr, &prog_data->base.vue_map,
|
|
MESA_SHADER_TESS_EVAL);
|
|
}
|
|
|
|
const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8;
|
|
fs_visitor v(compiler, ¶ms->base, &key->base,
|
|
&prog_data->base.base, nir, dispatch_width,
|
|
params->base.stats != NULL, debug_enabled);
|
|
if (!v.run_tes()) {
|
|
params->base.error_str =
|
|
ralloc_strdup(params->base.mem_ctx, v.fail_msg);
|
|
return NULL;
|
|
}
|
|
|
|
assert(v.payload().num_regs % reg_unit(devinfo) == 0);
|
|
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
|
|
|
|
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
|
|
|
|
fs_generator g(compiler, ¶ms->base,
|
|
&prog_data->base.base, MESA_SHADER_TESS_EVAL);
|
|
if (unlikely(debug_enabled)) {
|
|
g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
|
|
"%s tessellation evaluation shader %s",
|
|
nir->info.label ? nir->info.label
|
|
: "unnamed",
|
|
nir->info.name));
|
|
}
|
|
|
|
g.generate_code(v.cfg, dispatch_width, v.shader_stats,
|
|
v.performance_analysis.require(), params->base.stats);
|
|
|
|
g.add_const_data(nir->constant_data, nir->constant_data_size);
|
|
|
|
return g.get_assembly();
|
|
}
|