Ruijing Dong c1e52baf30 radeonsi/vcn: enable roi feature for vcn5 ... Compared to vcn4, qp map unit is a 32bit number, vcn5 uses 16bit integer number, in addition to that it has 2 unit alignment requirement(32 bit alignment) and each qp value needs left shift 7 bits. Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29423>		2024-05-30 20:12:37 +00:00
..
ci	…
glsl_tests	…
driinfo_radeonsi.h	…
gfx10_shader_ngg.c	…
gfx11_query.c	…
meson.build	build/amd: add amd-use-llvm build option	2024-05-30 19:05:00 +00:00
pspdecryptionparam.h	…
radeon_temporal.h	…
radeon_uvd.c	…
radeon_uvd.h	…
radeon_uvd_enc.c	…
radeon_uvd_enc.h	…
radeon_uvd_enc_1_1.c	…
radeon_vce.c	…
radeon_vce.h	…
radeon_vce_40_2_2.c	…
radeon_vce_50.c	…
radeon_vce_52.c	…
radeon_vcn.c	…
radeon_vcn.h	…
radeon_vcn_dec.c	radeonsi/vcn: Avoid copy when resizing bitstream buffer	2024-05-27 13:28:54 +00:00
radeon_vcn_dec.h	…
radeon_vcn_dec_jpeg.c	…
radeon_vcn_enc.c	radeonsi/vcn: enable roi feature for vcn5	2024-05-30 20:12:37 +00:00
radeon_vcn_enc.h	radeonsi/vcn: enable av1 encoding in vcn5	2024-05-30 20:12:37 +00:00
radeon_vcn_enc_1_2.c	radeonsi/vcn: enable roi feature for vcn5	2024-05-30 20:12:37 +00:00
radeon_vcn_enc_2_0.c	…
radeon_vcn_enc_3_0.c	…
radeon_vcn_enc_4_0.c	radeonsi/vcn: share functions between vcn4/vcn5	2024-05-30 20:12:37 +00:00
radeon_vcn_enc_5_0.c	radeonsi/vcn: enable av1 encoding in vcn5	2024-05-30 20:12:37 +00:00
radeon_video.c	…
radeon_video.h	…
si_blit.c	…
si_buffer.c	…
si_build_pm4.h	…
si_clear.c	ac,radv,radeonsi: add function to determine if alpha should be on MSB	2024-05-22 08:17:31 +02:00
si_compute.c	…
si_compute_blit.c	radeonsi/gfx12: fix incorrect condition for when to do clear_buffer via compute	2024-05-24 13:48:28 +00:00
si_cp_dma.c	…
si_cp_reg_shadowing.c	…
si_debug.c	…
si_debug_options.h	…
si_descriptors.c	radeonsi: use common build buffer descriptor helpers	2024-05-27 08:17:58 +02:00
si_fence.c	…
si_get.c	radeonsi/vcn: correct tile_size_bytes_minus1	2024-05-30 20:12:37 +00:00
si_gfx_cs.c	…
si_gpu_load.c	…
si_nir_lower_abi.c	radeonsi: use common build buffer descriptor helpers	2024-05-27 08:17:58 +02:00
si_nir_lower_resource.c	radeonsi: use common build buffer descriptor helpers	2024-05-27 08:17:58 +02:00
si_nir_lower_vs_inputs.c	…
si_nir_optim.c	…
si_perfcounter.c	…
si_perfetto.cpp	…
si_perfetto.h	…
si_pipe.c	build/amd: add amd-use-llvm build option	2024-05-30 19:05:00 +00:00
si_pipe.h	radeonsi: use the common helper for initializing CB surfaces	2024-05-27 17:04:27 +02:00
si_pm4.c	…
si_pm4.h	…
si_public.h	…
si_query.c	…
si_query.h	…
si_sdma_copy_image.c	ac,radv,radeonsi: add function to determine if alpha should be on MSB	2024-05-22 08:17:31 +02:00
si_shader.c	build/amd: add amd-use-llvm build option	2024-05-30 19:05:00 +00:00
si_shader.h	…
si_shader_aco.c	…
si_shader_info.c	…
si_shader_internal.h	…
si_shader_llvm.c	…
si_shader_llvm.h	…
si_shader_llvm_gs.c	…
si_shader_llvm_ps.c	…
si_shader_llvm_tess.c	…
si_shader_nir.c	radeonsi: call nir_lower_int64 later to fix ACO failure with Tomb Raider	2024-05-21 18:20:30 +00:00
si_shaderlib_nir.c	…
si_sqtt.c	…
si_state.c	ac,radv,radeonsi: a function that sets mutable CB surface fields	2024-05-28 08:49:53 +00:00
si_state.h	…
si_state_binning.c	…
si_state_draw.cpp	…
si_state_msaa.c	…
si_state_shaders.cpp	build/amd: add amd-use-llvm build option	2024-05-30 19:05:00 +00:00
si_state_streamout.c	…
si_state_viewport.c	…
si_test_dma_perf.c	…
si_test_image_copy_region.c	…
si_texture.c	ac,radv,radeonsi: add ac_gpu_info::has_tc_compatible_htile	2024-05-30 11:05:03 +00:00
si_tracepoints.py	u_trace: extend tracepoint end_of_pipe bit into flags	2024-05-30 06:38:04 +00:00
si_utrace.c	u_trace: extend tracepoint end_of_pipe bit into flags	2024-05-30 06:38:04 +00:00
si_utrace.h	…
si_uvd.c	…
si_vpe.c	…
si_vpe.h	…