mirror of https://gitlab.freedesktop.org/mesa/mesa
309 lines
9.1 KiB
C
309 lines
9.1 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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* Copyright 2020 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "ac_sqtt.h"
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#include "ac_gpu_info.h"
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#include "util/u_math.h"
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#include "util/os_time.h"
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uint64_t
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ac_sqtt_get_info_offset(unsigned se)
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{
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return sizeof(struct ac_sqtt_data_info) * se;
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}
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uint64_t
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ac_sqtt_get_data_offset(const struct radeon_info *rad_info, const struct ac_sqtt *data, unsigned se)
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{
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unsigned max_se = rad_info->max_se;
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uint64_t data_offset;
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data_offset = align64(sizeof(struct ac_sqtt_data_info) * max_se, 1 << SQTT_BUFFER_ALIGN_SHIFT);
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data_offset += data->buffer_size * se;
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return data_offset;
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}
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uint64_t
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ac_sqtt_get_info_va(uint64_t va, unsigned se)
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{
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return va + ac_sqtt_get_info_offset(se);
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}
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uint64_t
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ac_sqtt_get_data_va(const struct radeon_info *rad_info, const struct ac_sqtt *data, uint64_t va,
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unsigned se)
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{
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return va + ac_sqtt_get_data_offset(rad_info, data, se);
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}
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void
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ac_sqtt_init(struct ac_sqtt *data)
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{
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list_inithead(&data->rgp_pso_correlation.record);
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simple_mtx_init(&data->rgp_pso_correlation.lock, mtx_plain);
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list_inithead(&data->rgp_loader_events.record);
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simple_mtx_init(&data->rgp_loader_events.lock, mtx_plain);
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list_inithead(&data->rgp_code_object.record);
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simple_mtx_init(&data->rgp_code_object.lock, mtx_plain);
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list_inithead(&data->rgp_clock_calibration.record);
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simple_mtx_init(&data->rgp_clock_calibration.lock, mtx_plain);
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list_inithead(&data->rgp_queue_info.record);
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simple_mtx_init(&data->rgp_queue_info.lock, mtx_plain);
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list_inithead(&data->rgp_queue_event.record);
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simple_mtx_init(&data->rgp_queue_event.lock, mtx_plain);
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}
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void
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ac_sqtt_finish(struct ac_sqtt *data)
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{
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assert(data->rgp_pso_correlation.record_count == 0);
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simple_mtx_destroy(&data->rgp_pso_correlation.lock);
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assert(data->rgp_loader_events.record_count == 0);
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simple_mtx_destroy(&data->rgp_loader_events.lock);
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assert(data->rgp_code_object.record_count == 0);
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simple_mtx_destroy(&data->rgp_code_object.lock);
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assert(data->rgp_clock_calibration.record_count == 0);
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simple_mtx_destroy(&data->rgp_clock_calibration.lock);
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assert(data->rgp_queue_info.record_count == 0);
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simple_mtx_destroy(&data->rgp_queue_info.lock);
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assert(data->rgp_queue_event.record_count == 0);
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simple_mtx_destroy(&data->rgp_queue_event.lock);
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}
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bool
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ac_is_sqtt_complete(const struct radeon_info *rad_info, const struct ac_sqtt *data,
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const struct ac_sqtt_data_info *info)
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{
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if (rad_info->gfx_level >= GFX10) {
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/* GFX10 doesn't have THREAD_TRACE_CNTR but it reports the number of
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* dropped bytes per SE via THREAD_TRACE_DROPPED_CNTR. Though, this
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* doesn't seem reliable because it might still report non-zero even if
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* the SQTT buffer isn't full.
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*
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* The solution here is to compare the number of bytes written by the hw
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* (in units of 32 bytes) to the SQTT buffer size. If it's equal, that
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* means that the buffer is full and should be resized.
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*/
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return !(info->cur_offset * 32 == data->buffer_size - 32);
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}
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/* Otherwise, compare the current thread trace offset with the number
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* of written bytes.
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*/
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return info->cur_offset == info->gfx9_write_counter;
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}
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uint32_t
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ac_get_expected_buffer_size(struct radeon_info *rad_info, const struct ac_sqtt_data_info *info)
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{
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if (rad_info->gfx_level >= GFX10) {
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uint32_t dropped_cntr_per_se = info->gfx10_dropped_cntr / rad_info->max_se;
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return ((info->cur_offset * 32) + dropped_cntr_per_se) / 1024;
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}
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return (info->gfx9_write_counter * 32) / 1024;
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}
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bool
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ac_sqtt_add_pso_correlation(struct ac_sqtt *sqtt, uint64_t pipeline_hash, uint64_t api_hash)
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{
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struct rgp_pso_correlation *pso_correlation = &sqtt->rgp_pso_correlation;
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struct rgp_pso_correlation_record *record;
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record = malloc(sizeof(struct rgp_pso_correlation_record));
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if (!record)
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return false;
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record->api_pso_hash = api_hash;
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record->pipeline_hash[0] = pipeline_hash;
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record->pipeline_hash[1] = pipeline_hash;
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memset(record->api_level_obj_name, 0, sizeof(record->api_level_obj_name));
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simple_mtx_lock(&pso_correlation->lock);
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list_addtail(&record->list, &pso_correlation->record);
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pso_correlation->record_count++;
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simple_mtx_unlock(&pso_correlation->lock);
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return true;
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}
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bool
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ac_sqtt_add_code_object_loader_event(struct ac_sqtt *sqtt, uint64_t pipeline_hash,
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uint64_t base_address)
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{
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struct rgp_loader_events *loader_events = &sqtt->rgp_loader_events;
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struct rgp_loader_events_record *record;
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record = malloc(sizeof(struct rgp_loader_events_record));
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if (!record)
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return false;
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record->loader_event_type = RGP_LOAD_TO_GPU_MEMORY;
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record->reserved = 0;
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record->base_address = base_address & 0xffffffffffff;
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record->code_object_hash[0] = pipeline_hash;
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record->code_object_hash[1] = pipeline_hash;
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record->time_stamp = os_time_get_nano();
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simple_mtx_lock(&loader_events->lock);
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list_addtail(&record->list, &loader_events->record);
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loader_events->record_count++;
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simple_mtx_unlock(&loader_events->lock);
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return true;
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}
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bool
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ac_sqtt_add_clock_calibration(struct ac_sqtt *sqtt, uint64_t cpu_timestamp, uint64_t gpu_timestamp)
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{
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struct rgp_clock_calibration *clock_calibration = &sqtt->rgp_clock_calibration;
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struct rgp_clock_calibration_record *record;
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record = malloc(sizeof(struct rgp_clock_calibration_record));
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if (!record)
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return false;
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record->cpu_timestamp = cpu_timestamp;
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record->gpu_timestamp = gpu_timestamp;
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simple_mtx_lock(&clock_calibration->lock);
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list_addtail(&record->list, &clock_calibration->record);
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clock_calibration->record_count++;
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simple_mtx_unlock(&clock_calibration->lock);
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return true;
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}
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/* See https://gitlab.freedesktop.org/mesa/mesa/-/issues/5260
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* On some HW SQTT can hang if we're not in one of the profiling pstates. */
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bool
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ac_check_profile_state(const struct radeon_info *info)
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{
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char path[128];
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char data[128];
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int n;
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if (!info->pci.valid)
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return false; /* Unknown but optimistic. */
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snprintf(path, sizeof(path),
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"/sys/bus/pci/devices/%04x:%02x:%02x.%x/power_dpm_force_performance_level",
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info->pci.domain, info->pci.bus, info->pci.dev, info->pci.func);
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FILE *f = fopen(path, "r");
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if (!f)
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return false; /* Unknown but optimistic. */
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n = fread(data, 1, sizeof(data) - 1, f);
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fclose(f);
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data[n] = 0;
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return strstr(data, "profile") == NULL;
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}
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union rgp_sqtt_marker_cb_id
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ac_sqtt_get_next_cmdbuf_id(struct ac_sqtt *data, enum amd_ip_type ip_type)
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{
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union rgp_sqtt_marker_cb_id cb_id = {0};
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cb_id.global_cb_id.cb_index =
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p_atomic_inc_return(&data->cmdbuf_ids_per_queue[ip_type]);
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return cb_id;
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}
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bool
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ac_sqtt_se_is_disabled(const struct radeon_info *info, unsigned se)
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{
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/* No active CU on the SE means it is disabled. */
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return info->cu_mask[se][0] == 0;
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}
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uint32_t
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ac_sqtt_get_active_cu(const struct radeon_info *info, unsigned se)
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{
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uint32_t cu_index;
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if (info->gfx_level >= GFX11) {
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/* GFX11 seems to operate on the last active CU. */
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cu_index = util_last_bit(info->cu_mask[se][0]) - 1;
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} else {
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/* Default to the first active CU. */
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cu_index = ffs(info->cu_mask[se][0]);
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}
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return cu_index;
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}
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bool
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ac_sqtt_get_trace(struct ac_sqtt *data, const struct radeon_info *info,
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struct ac_sqtt_trace *sqtt_trace)
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{
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unsigned max_se = info->max_se;
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void *ptr = data->ptr;
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memset(sqtt_trace, 0, sizeof(*sqtt_trace));
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for (unsigned se = 0; se < max_se; se++) {
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uint64_t info_offset = ac_sqtt_get_info_offset(se);
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uint64_t data_offset = ac_sqtt_get_data_offset(info, data, se);
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void *info_ptr = (uint8_t *)ptr + info_offset;
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void *data_ptr = (uint8_t *)ptr + data_offset;
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struct ac_sqtt_data_info *trace_info = (struct ac_sqtt_data_info *)info_ptr;
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struct ac_sqtt_data_se data_se = {0};
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int active_cu = ac_sqtt_get_active_cu(info, se);
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if (ac_sqtt_se_is_disabled(info, se))
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continue;
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if (!ac_is_sqtt_complete(info, data, trace_info))
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return false;
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data_se.data_ptr = data_ptr;
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data_se.info = *trace_info;
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data_se.shader_engine = se;
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/* RGP seems to expect units of WGP on GFX10+. */
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data_se.compute_unit = info->gfx_level >= GFX10 ? (active_cu / 2) : active_cu;
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sqtt_trace->traces[sqtt_trace->num_traces] = data_se;
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sqtt_trace->num_traces++;
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}
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sqtt_trace->rgp_code_object = &data->rgp_code_object;
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sqtt_trace->rgp_loader_events = &data->rgp_loader_events;
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sqtt_trace->rgp_pso_correlation = &data->rgp_pso_correlation;
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sqtt_trace->rgp_queue_info = &data->rgp_queue_info;
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sqtt_trace->rgp_queue_event = &data->rgp_queue_event;
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sqtt_trace->rgp_clock_calibration = &data->rgp_clock_calibration;
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return true;
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}
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uint32_t
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ac_sqtt_get_shader_mask(const struct radeon_info *info)
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{
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unsigned shader_mask = 0x7f; /* all shader stages */
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if (info->gfx_level >= GFX11) {
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/* Disable unsupported hw shader stages */
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shader_mask &= ~(0x02 /* VS */ | 0x08 /* ES */ | 0x20 /* LS */);
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}
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return shader_mask;
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}
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