mirror of https://gitlab.freedesktop.org/mesa/mesa
215 lines
6.4 KiB
C
215 lines
6.4 KiB
C
/*
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* Copyright 2019 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_SHADER_ARGS_H
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#define AC_SHADER_ARGS_H
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#include <stdbool.h>
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#include <stdint.h>
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/* Maximum dwords of inline push constants when the indirect path is still used */
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#define AC_MAX_INLINE_PUSH_CONSTS_WITH_INDIRECT 8
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/* Maximum dwords of inline push constants when the indirect path is not used */
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#define AC_MAX_INLINE_PUSH_CONSTS 32
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enum ac_arg_regfile
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{
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AC_ARG_SGPR,
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AC_ARG_VGPR,
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};
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enum ac_arg_type
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{
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AC_ARG_INVALID = -1,
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AC_ARG_FLOAT,
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AC_ARG_INT,
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AC_ARG_CONST_PTR, /* Pointer to i8 array */
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AC_ARG_CONST_FLOAT_PTR, /* Pointer to f32 array */
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AC_ARG_CONST_PTR_PTR, /* Pointer to pointer to i8 array */
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AC_ARG_CONST_DESC_PTR, /* Pointer to v4i32 array */
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AC_ARG_CONST_IMAGE_PTR, /* Pointer to v8i32 array */
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};
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struct ac_arg {
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uint16_t arg_index;
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bool used;
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};
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#define AC_MAX_ARGS 384 /* including all VS->TCS IO */
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struct ac_shader_args {
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/* Info on how to declare arguments */
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struct {
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enum ac_arg_type type;
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enum ac_arg_regfile file;
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uint8_t offset;
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uint8_t size;
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bool skip : 1;
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bool pending_vmem : 1; /* Loaded from VMEM and needs waitcnt before use. */
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bool preserved : 1;
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} args[AC_MAX_ARGS];
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uint16_t arg_count;
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uint16_t num_sgprs_used;
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uint16_t num_vgprs_used;
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uint16_t return_count;
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uint16_t num_sgprs_returned;
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uint16_t num_vgprs_returned;
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/* User data 0/1. GFX: descriptor list, Compute: scratch BO. These are the SGPRs used by RADV for
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* scratch and have to be accessed using llvm.amdgcn.implicit.buffer.ptr for LLVM in that case.
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*/
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struct ac_arg ring_offsets;
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/* VS */
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struct ac_arg base_vertex;
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struct ac_arg start_instance;
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struct ac_arg draw_id;
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struct ac_arg vertex_buffers;
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struct ac_arg vertex_id;
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struct ac_arg vs_rel_patch_id;
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struct ac_arg vs_prim_id;
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struct ac_arg instance_id;
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/* Merged shaders */
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struct ac_arg tess_offchip_offset;
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struct ac_arg merged_wave_info;
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/* On gfx10:
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* - bits 0..11: ordered_wave_id
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* - bits 12..20: number of vertices in group
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* - bits 22..30: number of primitives in group
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*/
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struct ac_arg gs_tg_info;
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struct ac_arg scratch_offset;
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/* TCS */
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struct ac_arg tcs_factor_offset;
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struct ac_arg tcs_wave_id; /* gfx11+ */
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struct ac_arg tcs_patch_id;
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struct ac_arg tcs_rel_ids;
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/* TES */
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struct ac_arg tes_u;
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struct ac_arg tes_v;
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struct ac_arg tes_rel_patch_id;
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struct ac_arg tes_patch_id;
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/* GS */
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struct ac_arg es2gs_offset; /* separate legacy ES */
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struct ac_arg gs2vs_offset; /* legacy GS */
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struct ac_arg gs_wave_id; /* legacy GS */
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struct ac_arg gs_attr_offset; /* gfx11+: attribute ring offset in 512B increments */
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/* GS vertex indices/offsets:
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*
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* GFX6-8: [0-5] 6x uint32, multiplied by VGT_ESGS_RING_ITEMSIZE by hw
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* GFX9-11 non-passthrough: [0-2] 6x packed uint16, multiplied by VGT_ESGS_RING_ITEMSIZE by hw
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*
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* GFX10-11 passthrough: [0] 1x uint32 with the following bitfields matching the prim export:
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* [0:8] vertex index 0
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* [9] edgeflag 0
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* [10:18] vertex index 1
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* [19] edgeflag 1
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* [20:28] vertex index 2
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* [29] edgeflag 2
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* [31] 0 (valid prim)
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*
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* GFX12+: [0-1] 2x uint32 with the following bitfields matching the prim export except
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* the GS invocation ID, which is 0 without a user GS, so it doesn't have to be masked
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* out for the prim export:
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* [0]:
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* [0:7] vertex index 0
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* [8] edgeflag 0
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* [9:16] vertex index 1
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* [17] edgeflag 1
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* [18:25] vertex index 2
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* [26] edgeflag 2
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* [27:31] GS invocation ID
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* [1]:
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* [0:7] vertex index 3
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* [9:16] vertex index 4
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* [18:25] vertex index 5
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*/
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struct ac_arg gs_vtx_offset[6];
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struct ac_arg gs_prim_id;
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struct ac_arg gs_invocation_id; /* GFX6-11 only. GFX12+ uses gs_vtx_offset[0]. */
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/* Streamout */
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struct ac_arg streamout_config;
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struct ac_arg streamout_write_index;
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struct ac_arg streamout_offset[4];
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/* PS */
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struct ac_arg frag_pos[4];
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struct ac_arg front_face;
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struct ac_arg ancillary;
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struct ac_arg sample_coverage;
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struct ac_arg prim_mask;
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struct ac_arg pops_collision_wave_id;
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struct ac_arg load_provoking_vtx;
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struct ac_arg persp_sample;
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struct ac_arg persp_center;
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struct ac_arg persp_centroid;
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struct ac_arg pull_model;
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struct ac_arg linear_sample;
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struct ac_arg linear_center;
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struct ac_arg linear_centroid;
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struct ac_arg pos_fixed_pt;
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/* CS */
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struct ac_arg local_invocation_ids;
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struct ac_arg num_work_groups;
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/* GFX6-11 only. GFX12+ uses read only SGPRs {TTMP9[0:31], TTMP7[0:15], TTMP7[16:31]}. */
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struct ac_arg workgroup_ids[3];
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struct ac_arg tg_size;
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/* Mesh and task shaders */
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struct ac_arg task_ring_entry; /* Pointer into the draw and payload rings. */
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/* Vulkan only */
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struct ac_arg push_constants;
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struct ac_arg inline_push_consts[AC_MAX_INLINE_PUSH_CONSTS];
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uint64_t inline_push_const_mask;
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struct ac_arg view_index;
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struct ac_arg force_vrs_rates;
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/* RT */
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struct {
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struct ac_arg uniform_shader_addr;
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struct ac_arg sbt_descriptors;
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struct ac_arg launch_sizes[3];
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struct ac_arg launch_size_addr;
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struct ac_arg launch_ids[3];
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struct ac_arg dynamic_callable_stack_base;
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struct ac_arg traversal_shader_addr;
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struct ac_arg shader_addr;
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struct ac_arg shader_record;
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struct ac_arg payload_offset;
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struct ac_arg ray_origin;
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struct ac_arg ray_tmin;
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struct ac_arg ray_direction;
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struct ac_arg ray_tmax;
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struct ac_arg cull_mask_and_flags;
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struct ac_arg sbt_offset;
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struct ac_arg sbt_stride;
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struct ac_arg miss_index;
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struct ac_arg accel_struct;
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struct ac_arg primitive_id;
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struct ac_arg instance_addr;
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struct ac_arg geometry_id_and_flags;
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struct ac_arg hit_kind;
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} rt;
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};
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void ac_add_arg(struct ac_shader_args *info, enum ac_arg_regfile regfile, unsigned registers,
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enum ac_arg_type type, struct ac_arg *arg);
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void ac_add_return(struct ac_shader_args *info, enum ac_arg_regfile regfile);
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void ac_add_preserved(struct ac_shader_args *info, const struct ac_arg *arg);
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void ac_compact_ps_vgpr_args(struct ac_shader_args *info, uint32_t spi_ps_input);
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#endif
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