Commit Graph

104478 Commits

Author SHA1 Message Date
Marek Olšák 1cf3631b9c mesa: expose ARB_post_depth_coverage in the Compatibility profile
It only contains GLSL changes.

v2: allow the layout qualifier on GLSL <= 1.30
2018-08-24 00:36:18 -04:00
Jason Ekstrand 8d8222461f intel/nir: Enable nir_opt_find_array_copies
We have to be a bit careful with this one because we want it to run in
the optimization loop but only in the first brw_nir_optimize call.
Later calls assume that we've lowered away copy_deref instructions and
we don't want to introduce any more.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15176942 -> 15176942 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

In spite of the lack of any shader-db improvement, this patch completely
eliminates spilling in the Batman: Arkham City tessellation shaders.
This is because we are now able to detect that the temporary array
created by DXVK for storing TCS inputs is a copy of the input arrays and
use indirect URB reads instead of making a copy of 4.5 KiB of input data
and then indirecting on it with if-ladders.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:47:51 -05:00
Jason Ekstrand 53072582dc nir: Add an array copy optimization
This peephole optimization looks for a series of load/store_deref or
copy_deref instructions that copy an array from one variable to another
and turns it into a copy_deref that copies the entire array.  The
pattern it looks for is extremely specific but it's good enough to pick
up on the input array copies in DXVK and should also be able to pick up
the sequence generated by spirv_to_nir for a OpLoad of a large composite
followed by OpStore.  It can always be improved later if needed.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:47:47 -05:00
Jason Ekstrand a4a9c07549 intel/nir: Use nir_shrink_vec_array_vars
Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177605 -> 15176765 (<.01%)
    instructions in affected programs: 4259 -> 3419 (-19.72%)
    helped: 1
    HURT: 0

    total spills in shared programs: 10954 -> 10855 (-0.90%)
    spills in affected programs: 295 -> 196 (-33.56%)
    helped: 1
    HURT: 0

    total fills in shared programs: 22222 -> 22117 (-0.47%)
    fills in affected programs: 417 -> 312 (-25.18%)
    helped: 1
    HURT: 0

The helped shader is from the OglCSDof synmark test.  On my Kaby Lake
laptop, the actual framerate of the benchmark didn't appear to improve
beyond the noise.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:46:56 -05:00
Jason Ekstrand be8d009908 nir: Add a array-of-vector variable shrinking pass
This pass looks for variables with vector or array-of-vector types and
narrows the type to only the components used.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:46:56 -05:00
Jason Ekstrand 02a5442dd7 intel/nir: Use the new structure and array splitting passes
We call structure splitting once because it is guaranteed to split all
the structures in the entire shader in one go.  We call array splitting
in the loop in case future optimizations turn indirects into direct
dereferences and we can split more arrays.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177605 -> 15177605 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

This is unsurprising because nir_lower_vars_to_ssa already effectively
does structure and array splitting internally.  It doesn't actually
split the variables but it's ability to reason about aliasing in the
presence of arrays and structures and pick out scalars or vectors to be
lowered to SSA values is fairly advanced.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand fa6417495c nir: Add an array splitting pass
This pass looks for array variables where at least one level of the
array is never indirected and splits it into multiple smaller variables.

This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through arrays of arrays and can detect indirects on just
one level or even see that arr[i][0][5] does not alias arr[i][1][j].
This pass exists to help other passes more easily see through arrays of
arrays.  If a back-end does implement arrays using scratch or indirects
on registers, having more smaller arrays is likely to have better memory
efficiency.

v2 (Jason Ekstrand):
 - Better comments and naming (some from Caio)
 - Rework to use one hash map instead of two

v2.1 (Jason Ekstrand):
 - Fix a couple of bugs that were added in the rework including one
   which basically prevented it from running

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand 26eb077ec4 nir: Add a structure splitting pass
This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through structures and considers them to be "split".  This
pass exists to help other passes more easily see through structure
variables.  If a back-end does implement arrays using scratch or
indirects on registers, having more smaller arrays is likely to have
better memory efficiency.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand b489998e63 nir/types: Add array_or_matrix helpers
Reviewed-by: Thomas Helland<thomashelland90@gmail.com>
2018-08-23 21:44:14 -05:00
Kenneth Graunke b03dcb1e5f i965: don't include compute resources in "Combined" limits
The combined limits should only include shader stages that can be active
at the same time.  We don't need to include compute.

See also cff290df4c for st/mesa.

Unbreaks i965 from assert failing on driver load since Marek's
45f87a48f9, which dropped the core
Mesa capabilities before adjusting driver limits down to match.
2018-08-23 17:27:27 -07:00
Marek Olšák 9176703788 radeonsi: increase the maximum UBO size to 2 GB
Same as the closed driver.

This causes a failure in GL45-CTS.compute_shader.max, which has a trivial
bug.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 5693ca865d radeonsi: bump MAX_GS_INVOCATIONS
same as the closed driver

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák d3c1b212bc gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZE
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák f6ccd594e7 gallium: add PIPE_CAP_MAX_GS_INVOCATIONS
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 8c71b70f07 tgsi/ureg: don't call tgsi_sanity when it's too slow
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 80aecad0ca st/mesa: fix up uniform limits to be able to expose large UBOs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák cff290df4c st/mesa: don't include compute resources in "Combined" limits
The combined limits should only include shader stages that can be active
at the same time.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák d36af3a9d9 st/mesa: set ctx->Const.SubPixelBits
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 3867af39f9 glsl: fix error checking against MAX_UNIFORM_LOCATIONS
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák f01338118c mesa: make MaxCombinedUniformComponents 64-bit to allow large UBOs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák a8b71f2db8 mesa: add ctx->Const.MaxGeometryShaderInvocations
radeonsi wants to report a different value

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 45f87a48f9 mesa: don't include compute resources in MAX_COMBINED_* limits
5 is the maximum number of shader stages that can be used by 1 execution
call at the same time (e.g. a draw call). The limit ensures that each
stage can use all of its binding points.

Compute is separate and doesn't need the 5x multiplier.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 095515e16c mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES
same number as our closed GL driver

v2: don't use MaxArrayLockSize

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 356ff963ec mesa: remove incorrect change for EXT_disjoint_timer_query
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák 37eee90df7 glapi: actually implement GL_EXT_robustness for GLES
The extension was exposed but not the functions.

This fixes:
    dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.readn_pixels
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformfv
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformiv

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-08-23 16:54:30 -04:00
Kenneth Graunke 578e45ab7b intel/decoder: Decode SFIXED values.
This lets us example SAMPLER_STATE's LOD Bias field, among other things.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-23 13:04:53 -07:00
Emil Velikov 855af9a5a2 travis: use python3 for the autoconf builds
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 17:00:28 +01:00
Emil Velikov ae7898dfdb configure: allow building with python3
Pretty much all of the scripts are python2+3 compatible.
Check and allow using python3, while adjusting the PYTHON2 refs.

Note:
 - python3.4 is used as it's the earliest supported version
 - python3 chosen prior to python2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 17:00:13 +01:00
Emil Velikov c51e7486d9 bin/git_sha1_gen.py: remove execute bit/shebang
The script is executed explicitly via the build system, that uses
PYTHON/prog_python and equivalent.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 17:00:04 +01:00
Eric Engestrom 993a456360 vk/wsi: avoid reading uninitialised memory
It will be ignored by x11_swapchain_result() anyway (because reaching
the `fail` label without setting `result` means the swapchain status was
already a hard error), but the compiler still complains about reading
uninitialised memory.

While at it, drop the unused assignment right before returning.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 14:47:59 +01:00
Eric Engestrom a0f6a11944 egl: drop unused _EGL_BUILT_IN_DRIVER_DRI2
Unused since b174a1ae72 "egl: Simplify the "driver" interface".

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-08-23 14:47:59 +01:00
Samuel Pitoiset 87fbc16e34 radv/gfx9: implement coherent shaders for VK_ACCESS_SHADER_READ_BIT
Single-sample color and single-sample depth (not stencil)
are coherent with shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
2018-08-23 15:42:56 +02:00
Mathieu Bridon 6027d354d1 bin/install_megadrivers.py: Remove shebang and executable bit
Since the script is never executed directly, but launched by Meson as an
argument to the Python interpreter, those are not needed any more.

In addition, they are the reason this script was missed when I moved the
Meson buildsystem to Python 3, so removing them helps avoiding future
confusion.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-23 12:12:06 +01:00
Mathieu Bridon 8c8fd0bb8e meson: Run the install script with Python 3
The script was being run directly as an executable, and it has a
Python 2 shebang.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-23 12:12:06 +01:00
Emil Velikov 48820ed8da glsl: remove execute bit and shebang from python tests
Just like the rest of the tree - these should be run either as part of
the build system check target, or at the very least with an explicitly
versioned python executable.

Fixes: db8cd8e367 ("glcpp/tests: Convert shell scripts to a python script")
Fixes: 97c28cb082 ("glsl/tests: Convert optimization-test.sh to pure python")
Fixes: 3b52d29227 ("glsl/tests: reimplement warnings-test in python")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 12:02:45 +01:00
Emil Velikov e39b916d0c docs: update required mako version
The requirement was bumped a while back, but we forgot to update the
docs.

Fixes: ed871af91c ("configure.ac: raise Mako required version to
0.8.0")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 12:02:45 +01:00
Emil Velikov e7149369bd configure: use distutils in ax_check_python_mako_module
Handling the version comparison by hand is a bad idea. Python has a handy
module distutils for that - use it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-08-23 11:59:48 +01:00
Emil Velikov df2042d99a configure: enforce python 2.7 with AM_PATH_PYTHON
Currently we use AC_CHECK_PROGS looking for python2.7, python2 and
finally python. That is due to the varying names used across the
different OS.

Use the handy AM_PATH_PYTHON which finds the correct name and checks for
the version.

Note: python2.7 has been an unofficial requirement for quite some time.
Update the docs to reflect that.

Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-23 11:55:55 +01:00
Ian Romanick c7c0b391ef i965: Enable INTEL_shader_atomic_float_minmax on Gen9+
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 59c17dbc6c i965: Sort Gen9+ extension enables
This is a strictly alphabetic sort, as is done in extensions_table.h
There are other options.  We should pick one and document it.  Right
now, this file is chaos.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick d515c75463 intel/compiler: Implement untyped atomic float min, max, and compare-swap dataport messages
v2: Split changes to the message type field to another patch.  Suggested
by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick f347348f8a intel/compiler: Expand untyped atomic message type field by a bit
This is necessary for a new Gen9 message type that will be added in the
next patch.  There are also Gen8 message types that need the extra bit
(mostly for bindless).

v2: Split off from the next patch.  Suggested by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick d628642a34 intel/compiler: Silence unused parameter warnings
src/intel/compiler/brw_disasm_info.c: In function ‘nir_print_instr’:
src/intel/compiler/brw_disasm_info.c:30:61: warning: unused parameter ‘instr’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                             ^~~~~
src/intel/compiler/brw_disasm_info.c:30:74: warning: unused parameter ‘fp’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                                          ^~
src/intel/compiler/brw_disasm.c: In function ‘src_ia1’:
src/intel/compiler/brw_disasm.c:850:18: warning: unused parameter ‘_reg_file’ [-Wunused-parameter]
         unsigned _reg_file,
                  ^~~~~~~~~
src/intel/compiler/brw_fs_surface_builder.cpp: In function ‘void brw::surface_access::emit_byte_scattered_write(const brw::fs_builder&, const fs_reg&, const fs_reg&, const fs_reg&, unsigned int, unsigned int, unsigned int, brw_predicate)’:
src/intel/compiler/brw_fs_surface_builder.cpp:193:57: warning: unused parameter ‘size’ [-Wunused-parameter]
                                 unsigned dims, unsigned size,
                                                         ^~~~

v2: Update commit message.  brw_fs_generator.cpp warnings were already
fixed by another patch.  Noticed by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 0842655ac6 nir: Add floating point atomic min, max, and compare-swap instrinsics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 69ce7baa9e nir: Add floating point atomic add instrinsics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick a390158d10 glsl: Add support for lowering shared-variable float atomics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 39bf3100ac glsl: Add support for lowering SSBO float atomics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 280ab4afa8 glsl: Add built-in functions for INTEL_shader_atomic_float_minmax
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick c9d52c83a4 mesa: Extension boilerplate for INTEL_shader_atomic_float_minmax
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick 346321a836 docs: Initial version of INTEL_shader_atomic_float_minmax spec
v2: Describe interactions with the capabilities added by
SPV_INTEL_shader_atomic_float_minmax

v3: Remove 64-bit float support.

v4: Explain NaN issues.  Explain issues with atomicMin(-0, +0) and
atomicMax(-0, +0).

v5: Fix whitespace issues noticed by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00