Commit Graph

15 Commits

Author SHA1 Message Date
Erik Faye-Lund ff05137c2d nir: introduce and use nir_component_mask
The BITFIELD_MASK() macro is intended for using with actual bitfields,
not with nir_component_mask_t. This means we do some extra work to
handle values that are invalid for nir_component_mask_t in the first
place.

This eliminates some warnings on Clang, where the compiler complains
about casting UINT32_MAX to UINT16_MAX.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15547>
2022-04-19 06:54:47 +00:00
Rhys Perry 7a7838529a nir/lower_non_uniform: allow lowering with vec2 handles
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>
2021-04-27 15:56:07 +00:00
Jason Ekstrand 1ba9c262fd nir: Add image atomic_fmin/fmax intrinsics
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
2021-03-18 00:13:40 +00:00
Rhys Perry 1fd8b46667 nir,spirv: add sparse image loads
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
2021-01-06 20:36:38 +00:00
Rhys Perry b1619109ca nir/lower_non_uniform: remove non_uniform flags after lowering
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5201>
2020-12-08 13:02:18 +00:00
Jason Ekstrand c47fe54bc7 nir/lower_non_uniform: Better handle non-derefs
In particular, if we have an index or bindless handle we were passing
the original handle which, technically, is uniform within the context of
the if.  However, we can save the back-end compiler some effort if we
pass it the result of the read_first_invocation().

(Rebased by Kenneth Graunke and Rhys Perry.)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7592>
2020-12-07 19:27:56 +00:00
Jason Ekstrand 0bf8d156a9 nir/lower_non_uniform: Refactor for better code organization
In theory, I don't think this is a functional change.  We should
generate the same code before and after.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7592>
2020-12-07 19:27:56 +00:00
Kenneth Graunke 562e07db38 nir/lower_non_uniform: Use nir_read_first_invocation helper.
We now have a general helper for this, and don't need to roll our own.

Suggested by Rhys Perry in the review for MR !7592.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7592>
2020-12-07 19:27:56 +00:00
Rhys Perry efba865c4c nir/lower_non_uniform: improve code with the same texture, sampler indices
NIR can't CSE the read_first_invocation intrinsics, so we can end up
creating iand(read_first_invocation(a) == a, read_first_invocation(a) == a)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3813>
2020-11-26 16:07:37 +00:00
Rhys Perry 5ef04d7982 nir/lower_non_uniform: lower image/texture instructions taking derefs
v2: always assert on the texture/sampler handle's num_components
v3: replicate the deref inside the loop
v4: remove a case of useless line wrapping

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-10-11 14:26:58 +00:00
Jason Ekstrand 951cf94521 nir: Add explicit signs to image min/max intrinsics
This better matches all the other atomic intrinsics such as those for
SSBOs and shared variables where the sign is part of the intrinsic
opcode.  Both generators (GLSL and SPIR-V) know the sign from the type
of the image variable or handle.  In SPIR-V, signed min/max are separate
opcodes from unsigned.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-21 17:19:55 +00:00
Lionel Landwerlin 366811bedb nir/lower_non_uniform: safely iterate over blocks
This fixes a problem where the same instruction gets replaced twice.
This was happening when the replaced instruction would be at the end
of a block.

Replacement of :

   if ssa_8 {
                ....
      intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
   }

Would be :

   if ssa_8 {
      loop {
         vec1 32 ssa_47 = intrinsic read_first_invocation (ssa_44) ()
         vec1 1 ssa_48 = ieq ssa_47, ssa_44
         if ssa_48 {
            loop {
               vec1 32 ssa_49 = intrinsic read_first_invocation (ssa_44) ()
               vec1 1 ssa_50 = ieq ssa_49, ssa_44
               if ssa_50 {
                  intrinsic bindless_image_store (ssa_44, ssa_16, ssa_0, ssa_15) (5, 0, 34836, 32) /* image_dim=Buf */ /* image_array=false */ /* format=34836 */ /* access=32 */
                  break
               } else {
        ....
   }

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bd5457641 ("nir: Add a lowering pass for non-uniform resource access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-28 20:23:16 +01:00
Lionel Landwerlin e04cf0b612 nir: lower_non_uniform_access: iterate over instructions safely
This pass moves instructions around and adds control-flow in the
middle of blocks. We need to use nir_foreach_instr_safe to ensure that
we iterate over instructions correctly anyway.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bd5457641 ("nir: Add a lowering pass for non-uniform resource access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-16 10:22:01 +01:00
Lionel Landwerlin 391a836e8f nir: fix lower_non_uniform_access pass
Obviously missing the instruction insertion into the SSA list.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 3bd5457641 ("nir: Add a lowering pass for non-uniform resource access")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-15 18:15:20 +00:00
Jason Ekstrand 3bd5457641 nir: Add a lowering pass for non-uniform resource access
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-25 15:00:36 -05:00