Now that everything is in place, we can actually take advantage of
preambles. This wins us a crude form of UBO pushing (accounting for most
of the win here), as well as its intended purpose of optimizing
uniform-on-uniform arithmetic.
shader-db results are excellent. The shader that's regressed for instruction
count is a fragment shader that solely consists of `gl_FragColor = uniform`,
which goes from a vectorized UBO load to four scalar moves. That's more
instructions (and more bytes) but presumably faster, since ALU should be much
cheaper than load/store.
total instructions in shared programs: 6502 -> 5764 (-11.35%)
instructions in affected programs: 5136 -> 4398 (-14.37%)
helped: 60
HURT: 1
helped stats (abs) min: 2.0 max: 47.0 x̄: 12.33 x̃: 8
helped stats (rel) min: 0.84% max: 34.48% x̄: 18.69% x̃: 21.05%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
95% mean confidence interval for instructions value: -14.69 -9.51
95% mean confidence interval for instructions %-change: -20.49% -15.20%
Instructions are helped.
total bytes in shared programs: 42186 -> 38310 (-9.19%)
bytes in affected programs: 33182 -> 29306 (-11.68%)
helped: 60
HURT: 1
helped stats (abs) min: 10.0 max: 272.0 x̄: 64.83 x̃: 50
helped stats (rel) min: 0.72% max: 30.00% x̄: 15.16% x̃: 16.67%
HURT stats (abs) min: 14.0 max: 14.0 x̄: 14.00 x̃: 14
HURT stats (rel) min: 31.82% max: 31.82% x̄: 31.82% x̃: 31.82%
95% mean confidence interval for bytes value: -77.73 -49.35
95% mean confidence interval for bytes %-change: -16.66% -12.11%
Bytes are helped.
total halfregs in shared programs: 2370 -> 1639 (-30.84%)
halfregs in affected programs: 1804 -> 1073 (-40.52%)
helped: 60
HURT: 0
helped stats (abs) min: 1.0 max: 40.0 x̄: 12.18 x̃: 8
helped stats (rel) min: 3.85% max: 72.73% x̄: 41.37% x̃: 36.17%
95% mean confidence interval for halfregs value: -14.77 -9.60
95% mean confidence interval for halfregs %-change: -46.00% -36.75%
Halfregs are helped.
Total CPU time (seconds): 2.71 -> 2.80 (3.32%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
This pass creates preamble shaders. The heavylifting is done by
nir_opt_preamble. We do need to define the cost model for nir_opt_preamble, set
up 16-bit units for the register file, and scalarize the resulting
load/store_preamble intrinsics.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
This does not seem to be possible architecturally. Exhaustively checked
all bits of the encoding. Avoids regressing
dEQP-GLES3.functional.texture.units.8_units.only_2d.0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
lower_resinfo generates some 64-bit math, so we need to handle it. Even
though we don't have native 64-bit moves, it's convenient to pretend we
do to avoid special cases in the IR. In particular, modelling 64-bit
mov_imm in the IR means our existing small constant propagation code
works, with zero-extension from 8->64.
Fixes dEQP-GLES3.functional.texture.units.2_units.only_2d_array.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
It's useful to be able to copyprop uniform registers into COLLECT. That
requires handling of uniform registers in the parallel copy lowering,
which isn't too hard to add.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
These need to copy values between GPRs and uniform registers. This is pretty
easy in either direction. This implements scalar versions of the intrinsics. A
backend NIR pass will scalarize for us.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
We really need to autogenerate the packing code... It's on the todo
list, currently in discussions on how to best go about this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
Needed for preambles. Make agx_context map to nir_function_impl and
the (out, key, binary) triple the only global shader state.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
The driver needs to plumb this information into the hardware. It will
also make it easier to preserve across preamble/main function in a
moment.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
Currently we don't have a good mechanism for this other than being
careful... assert() at least. The long term plan is to lift the
UBO/VBO lowerings into NIR, making the sysval requirements visible in
the NIR. (And possibly moving to a descriptor set model to better match
Vulkan? I need to talk to jekstrand about what we want to do here long
term.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
We need 9-bits to index into the uniform file. Fix an overflow and add
some asserts to try to catch these issues earlier.
Sigh, C.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
Extend the compiler/driver ABI to attach preambles, and plumb them into
the USC hardware when needed. This is the easy part!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
The big discovery is the "number of uniform registers" field. I learned
about this one accidentally when my preamble shaders weren't working
right, because we had inadvertently hardcoded "at most 32 registers" :-)
In the course of identifying that field, I found that the pipeline
address is used as a tagged pointer, with some unknown field in the
bottom bits and alignment demanded. The XML is updated to account for
this.
I later found that there's also a "number of general purpose registers
used by the preamble shader" field. I missed this one first, because the
encoding is slightly different from the usual "number of general purpose
registers in the main shader" field. The specification is slightly
coarser. I don't know why the hardware needs that
information anyway -- occupancy of the preamble shader should be
irrelevant -- but it's not a big deal.
Finally I found that the "more than 4 textures?" bit is... not that. I
do not yet know what it is, but it is... not that.
These all use the new groups() modifier for GenXML
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
The start field in the Uniform USC word is only 8-bits, whereas 9-bits
are required to address the entire uniform register file. This other
word gets used for the high half, with start indexed from u128l in
the natural way.
Apparently spending the evening stuffing too many uniforms into Metal is
paying off.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
This gets shader-db's runner working, in conjunction with a shader-db ./run
modified to set ASAHI_MESA_DEBUG=precompile. This flag triggers precompiles of
all shaders witha default key so we can exercise the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
It has not been used in quite some time but adds maintainence burden.
Its function is replaced by drm-shim in conjunction with shader-db's
./run, which goes through the actual driver.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
...Rather than reserving the union of the registers live-out of the
predecessors. This avoids reserving registers that are killed along a
control flow edge (where the predecessor has another successor that does
use the register).
glmark2 subset of shaderdb:
total instructions in shared programs: 6442 -> 6440 (-0.03%)
instructions in affected programs: 42 -> 40 (-4.76%)
helped: 1
HURT: 0
total bytes in shared programs: 42186 -> 42174 (-0.03%)
bytes in affected programs: 270 -> 258 (-4.44%)
helped: 1
HURT: 0
total halfregs in shared programs: 1769 -> 1757 (-0.68%)
halfregs in affected programs: 75 -> 63 (-16.00%)
helped: 3
HURT: 0
helped stats (abs) min: 4.0 max: 4.0 x̄: 4.00 x̃: 4
helped stats (rel) min: 16.00% max: 16.00% x̄: 16.00% x̃: 16.00%
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
This means we don't reserve the registers, which improves RA
considerably. Using a special preload psuedo-op instead of a regular
move allows us to constrain semantics and gaurantee coalescing.
shader-db on glmark2 subset:
total instructions in shared programs: 6448 -> 6442 (-0.09%)
instructions in affected programs: 230 -> 224 (-2.61%)
helped: 4
HURT: 0
total bytes in shared programs: 42232 -> 42196 (-0.09%)
bytes in affected programs: 1530 -> 1494 (-2.35%)
helped: 4
HURT: 0
total halfregs in shared programs: 2291 -> 1926 (-15.93%)
halfregs in affected programs: 2185 -> 1820 (-16.70%)
helped: 75
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
This makes the dataflow easier to read, especially with splits and
collects (which take variable numbers of sources/destinations).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
We know that phi nodes are always at the start (this is asserted in
agx_validate and a fundamental invariant of SSA form). That means we can
cheaply iterate all n phi nodes forward (or n non-phi nodes backwards)
in O(n) time. We already open code this idiom in a few places, use
common iterators instead so we don't need to justify in random places.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18804>
Alyssa Rosenzweig
Alyssa Rosenzweig