Commit Graph

104734 Commits

Author SHA1 Message Date
Christian Gmeiner 773d6ea6e7 imx: make use of loader_open_render_node(..) helper
Gets rid of hard-coded gpu device path.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-31 21:47:13 +02:00
Christian Gmeiner b05a8f4f41 tegra: make use loader_open_render_node(..) helper
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-31 21:46:32 +02:00
Christian Gmeiner ab348885eb loader: add loader_open_render_node(..)
This helper is almost a 1:1 copy of tegra_open_render_node().

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-31 21:46:03 +02:00
Christian Gmeiner d0b09e2dfe tegra: fix memory leak
Fixes: 1755f608f5 ("tegra: Initial support")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-31 21:45:16 +02:00
Daniel Stone 01c0aa9f05 st/dri: Don't expose sRGB formats to clients
Though the SARGB8888 format is used internally through its FourCC value,
it is not a real format as defined by drm_fourcc.h; it cannot be used
with KMS or other interfaces expecting drm_fourcc.h format codes.

Ensure we don't advertise it through the dmabuf format/modifier query
interfaces, preventing us from tripping over an assert.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reported-by: Michel Dänzer <michel.daenzer@amd.com>
Fixes: 8c1b9882b2 ("egl/dri2: Guard against invalid fourcc formats")
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
2018-08-31 18:02:42 +01:00
Samuel Pitoiset 686ec97cfb radv: add missing support for protected memory properties
Fixes Vulkan CTS CL#2849. Similar to the ANV driver.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-31 17:35:13 +02:00
Samuel Pitoiset 7355e9326b radv: remove dead code in scan_shader_output_decl()
Never used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset e9acf069b2 radv: remove radv_shader_context::num_output_{clips,culls}
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset a6a6441c75 radv: adjust the cull dist mask in scan_shader_output_decl()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset ea778e760c radv: get length of the clip/cull distances array from usage mask
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset 732679c25e radv: do not recompute the output usage mask for clipdist twice
The shader info pass takes care of this now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset 730c704f86 radv: gather the output usage mask for clip/cull distances correctly
It's a special case because both are combined into a single array.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset ffe3a2a298 radv: add set_output_usage_mask() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-08-31 17:34:41 +02:00
Samuel Pitoiset 6f47df3129 radv: fix passing clip/cull distances from VS to PS
CTS doesn't test input clip/cull distances for the fragment
shader stage, which explains why this was totally broken. I
wrote a simple test locally that works now.

This fixes a crash with GTA V and DXVK.

Note that we are exporting unused parameters from the vertex
shader now, but this can't be optimized easily because we don't
keep the fragment shader info...

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107477
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-31 17:34:36 +02:00
Juan A. Suarez Romero 54a9622dd5 egl/wayland: do not leak wl_buffer when it is locked
If color buffer is locked, do not set its wayland buffer to NULL;
otherwise it can not be freed later.

Rather, flag it in order to destroy it later on the release event.

v2: instruct release event to unlock only or free wl_buffer too (Daniel)

This also fixes dEQP-EGL.functional.swap_buffers_with_damage.* tests.

CC: Daniel Stone <daniel@fooishbar.org>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2018-08-31 16:29:36 +02:00
Dave Airlie 2c1f249f2b ac/radeonsi: fix CIK copy max size
While adding transfer queues to radv, I started writing some tests,
the first test I wrote fell over copying a buffer larger than this
limit.

Checked AMDVLK and found the correct limit.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-31 15:11:49 +10:00
Dave Airlie c9f5448695 radeonsi: fix regression in indirect input swizzles.
This fixes:
tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3.shader_test
since I reworked the 64-bit swizzles.

Fixes: bb17ae49ee (gallivm: allow to pass two swizzles into fetches.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-31 06:08:24 +01:00
Dave Airlie 750b829daf radeonsi: fix tess/gs fetchs for new swizzle.
I have piglit results from my machine, but I must have messed up,
and not built mesa in between properly.

Fixes: bb17ae49ee (gallivm: allow to pass two swizzles into fetches.)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-31 06:08:21 +01:00
Marek Olšák 355ed029b0 mesa: ignore VAO IDs equal to 0 in glDeleteVertexArrays
This fixes a firefox crash.

Fixes: 781a78914c

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-08-30 22:30:28 -04:00
Kenneth Graunke b147254d36 Revert "intel/tools/aubwrite: Always use physical addresses for traces."
This reverts commit f8cfc77660.

This appears to break intel_dump_gpu for Gen9 systems - I can load them
in the simulator, but nothing happens.  Reverting the patch makes the
simulator properly execute our commands and shaders again.
2018-08-30 14:36:28 -07:00
Jason Ekstrand a0f18f2142 intel/nir: Lowering image loads and stores trashes all metadata
This fixes the GL_ARB_fragment_shader_interlock piglit test on gen8
platforms where the lack of metadata dirtying was causing another pass
to accidentally delete a much needed loop.

https://bugs.freedesktop.org/show_bug.cgi?id=107745
Fixes: 37f7983bcc "intel/compiler: Do image load/store lowering..."
Jason Ekstrand <jason@jlekstrand.net> writes:
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-30 14:06:31 -05:00
Jason Ekstrand d9cf4308ce i965/screen: Allow modifiers on sRGB formats
This effectively reverts a266934935 which
was a misguided attempt at protecting intel_query_dma_buf_modifiers from
invalid formats.  Unfortunately, in some internal EGL cases, we can get
an SRGB format validly in this function.  Rejecting such formats caused
us to not allow CCS in some cases where we should have been allowing it.
This regressed the performance of some SynMark tests as well as GfxBench
ALU2, Tessellation and Manhattan 3.0 tests

There's some question of whether or not we really should be using SRGB
"fourcc" formats that aren't actually in drm_foucc.h but there's not
much harm in allowing them through here.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107223
Fixes: a266934935 "i965/screen: Return false for unsupported..."
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-30 11:41:50 -05:00
Jason Ekstrand 8c1b9882b2 egl/dri2: Guard against invalid fourcc formats
We already reject attempts to import images with invalid fourcc formats
but don't really guard the queries all that well.  This makes us error
out in any calls to eglQueryDmaBufModifiersEXT if the given format is
not a valid fourcc format.  We also add an assert to ensure that drivers
don't advertise any non-fourcc formats.

Cc: mesa-stable@lists.freedesktop.org
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-30 11:41:50 -05:00
Jason Ekstrand b95896f492 egl/dri2: Add a helper for the number of planes for a FOURCC format
This also serves as a convenient "is this a fourcc format" check as well
which we'll take advantage of in the next commit.

Cc: mesa-stable@lists.freedesktop.org
Tested-By: Eero Tamminen <eero.t.tamminen@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-30 11:41:50 -05:00
Jason Ekstrand 19bdc7dd0f radv/meta: Set num_components on image_store intrinsics
Now that image load/store intrinsics are variable-width, we need to set
num_components accordingly.  In 15d39f474b, both glsl_to_nir and
spirv_to_nir were updated to properly set num_components but radv meta
was left behind.

Fixes: 15d39f474b "nir: Make image load/store intrinsics..."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-30 08:26:14 -05:00
Vicki Pfau 8c0e3f3822 gallivm: Detect VSX separately from Altivec
Previously gallivm would attempt to use VSX instructions on all systems
where it detected that Altivec is supported; however, VSX was added to
POWER long after Altivec, causing lots of crashes on older POWER/PPC
hardware, e.g. PPC Macs. By detecting VSX separately from Altivec we can
automatically disable it on hardware that supports Altivec but not VSX

Signed-off-by: Vicki Pfau <vi@endrift.com>
2018-08-30 06:09:49 +02:00
Ilia Mirkin 3e04c67950 nv50: bump compat glsl level to same as core
Passes the compat piglits. I'm sure that there will be odd issues that
aren't caught by them, but at least it should basically work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-08-29 20:51:40 -04:00
Ilia Mirkin a608e5cc9f nvc0: bump compat GLSL version to match core
This passes the handful of tests in piglit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-08-29 20:51:40 -04:00
Ilia Mirkin 52a7297dc6 glsl: avoid lowering texcoord array except in simple cases
With compat creeping up to geometry and tess shaders, lowering texcoord
accesses/writes becomes more complicated. Since it's an optimization
anyways, just avoid the complication for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-08-29 20:51:23 -04:00
Andres Gomez 3731233cba docs: update calendar 18.2.0-rc5 is out, extend to 18.2.0-rc6
Signed-off-by: Andres Gomez <agomez@igalia.com>
2018-08-30 03:33:08 +03:00
Timothy Arceri 9c47c39687 st/mesa, gallium: add a workaround for No Mans Sky
The spec seems clear this is not allowed but the Nvidia binary
forces apps to add layout qualifiers so this works around the
issue for No Mans Sky until the CTS can be sorted out.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 09:54:40 +10:00
Timothy Arceri 9ce7d79cdc glsl: add a mechanism to allow layout qualifiers on function params
The spec is quite clear this is not allowed:

    From Section 4.4. (Layout Qualifiers) of the GLSL 4.60 spec:

       "Layout qualifiers can appear in several forms of declaration.
       They can appear as part of an interface block definition or
       block member, as shown in the grammar in the previous section.
       They can also appear with just an interface-qualifier to establish
       layouts of other declarations made with that qualifier:

          layout-qualifier interface-qualifier ;

       Or, they can appear with an individual variable declared with
       an interface qualifier:

          layout-qualifier interface-qualifier declaration ;"

    From Section 4.10 (Memory Qualifiers) of the GLSL 4.60 spec:

       "Layout qualifiers cannot be used on formal function parameters,
       and layout qualification is not included in parameter matching."

However on the Nvidia binary driver they actually fail to compile
if image function params don't have a layout qualifier. This results
in applications such as No Mans Sky using layout qualifiers on params.

I've submitted a CTS test to expose this problem in the Nvidia driver
but until that is resolved this patch will help Mesa drivers work
around the issue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 09:54:40 +10:00
Timothy Arceri 28a3731e3f glsl: skip stringification in preprocessor if in unreachable branch
This fixes compilation of some "No Mans Sky" shaders where the stringification
happens in branches intended for DX12.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-08-30 09:51:57 +10:00
Bas Nieuwenhuizen 4738b6ac81 radv: Add missing checks in radv_get_image_format_properties.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-08-30 01:21:20 +02:00
Dave Airlie bb17ae49ee gallivm: allow to pass two swizzles into fetches.
This hijacks the top 16-bits of swizzle, to pass in the swizzle
for the second channel.

This fixes handling .yx swizzles of 64-bit values.

This should fixup radeonsi and llvmpipe.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107524
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 00:15:40 +01:00
Timothy Arceri 3bcec6cf1c radeonsi: enable radeonsi_zerovram for No Mans Sky
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 07:57:38 +10:00
Timothy Arceri 5566dd8a61 radeonsi: add radeonsi_zerovram driconfig option
More and more games seem to require this so lets make it a config
option.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 07:57:38 +10:00
Timothy Arceri 406c3d748d radeonsi: enable GL 4.5 in compat profile
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 07:57:38 +10:00
Timothy Arceri 781a78914c mesa: enable ARB_direct_state_access in compat for GL3.1+
We could enable it for lower versions of GL but this allows us
to just use the existing version/extension checks that are already
used by the core profile.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-08-30 07:57:38 +10:00
Marek Olšák 93b8b987d0 radeonsi: add a thorough clear/copy_buffer benchmark 2018-08-29 15:31:42 -04:00
Marek Olšák 5914f5bd4a radeonsi: let internal compute dispatches tune WAVES_PER_SH 2018-08-29 15:31:42 -04:00
Marek Olšák c5442c1165 radeonsi: add TGSI_SEMANTIC_CS_USER_DATA for reading up to 4 SGPRs with TGSI 2018-08-29 15:31:42 -04:00
Marek Olšák d7250e4304 radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA_SI for measuring DMA on SI
DMA on SI doesn't support the timestamp packet, so it's emulated.
2018-08-29 15:31:42 -04:00
Marek Olšák c359880d8b radeonsi: add SI_QUERY_TIME_ELAPSED_SDMA for measuring SDMA performance 2018-08-29 15:31:42 -04:00
Marek Olšák 0c5429cc73 radeonsi: add flag L2_STREAM for minimal cache usage 2018-08-29 15:31:41 -04:00
Marek Olšák 8f6e06d160 gallium: add TGSI_MEMORY_STREAM_CACHE_POLICY
For internal radeonsi shaders.
2018-08-29 15:31:41 -04:00
Jason Ekstrand d8033d4083 intel/compiler: Remove surface_idx from brw_image_param
Now that the drivers are lowering to surface indices themselves, we no
longer need to push the surface index into the shader.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand 3cbc02e469 intel: Use TXS for image_size when we have a typed surface
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand 09f1de97a7 anv,i965: Lower away image derefs in the driver
Previously, the back-end compiler turn image access into magic uniform
reads and there was a complex contract between back-end compiler and
driver about setting up and filling out those params.  As of this
commit, both drivers now lower image_deref_load_param_intel intrinsics
to load_uniform intrinsics controlled by the driver and lower the other
image_deref_* intrinsics to image_* intrinsics which take an actual
binding table index.  There are still "magic" uniforms but they are now
added and controlled entirely by the driver and that contract no longer
spans components.

This also has the side-effect of making most image use compile-time
binding table indices.  Previously, all image access pulled the binding
table index from a uniform.  Part of the reason for this was that the
magic uniforms made it difficult to decouple binding table indices from
the uniforms and, since they are indexed completely differently
(especially in Vulkan), it was hard to pull them apart.  Now that the
driver is handling both, it's trivial to decouple the two and provide
actual binding table indices.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15166872 -> 15164293 (-0.02%)
    instructions in affected programs: 115834 -> 113255 (-2.23%)
    helped: 191
    HURT: 0

    total cycles in shared programs: 571311495 -> 571196465 (-0.02%)
    cycles in affected programs: 4757115 -> 4642085 (-2.42%)
    helped: 73
    HURT: 67

    total spills in shared programs: 10951 -> 10926 (-0.23%)
    spills in affected programs: 742 -> 717 (-3.37%)
    helped: 7
    HURT: 0

    total fills in shared programs: 22226 -> 22201 (-0.11%)
    fills in affected programs: 1146 -> 1121 (-2.18%)
    helped: 7
    HURT: 0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:03 -05:00
Jason Ekstrand 0de003be03 nir: Add handle/index-based image intrinsics
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-08-29 14:04:02 -05:00