Commit Graph

53833 Commits

Author SHA1 Message Date
Kenneth Graunke cd0acb1abe i965: Make it possible to create a cfg_t without a backend_visitor.
All we really need is a memory context and the instruction list; passing
a backend_visitor is just convenient at times.

This will be necessary two patches from now.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:34 -08:00
Kenneth Graunke 4d09fe938e i965/fs: Move uses of brw_compile from do_wm_prog to brw_wm_fs_emit.
The brw_compile structure is closely tied to the Gen4-7 hardware
encoding.  However, do_wm_prog is very generic: it just calls out to
get a compiled program and then uploads it.

This isn't ultimately where we want it, but it's a step in the right
direction: it's now closer to the code generator.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:34 -08:00
Kenneth Graunke 3417b2f2b2 i965/fs: Pass the brw_context pointer into fs_visitor explicitly.
We used to steal it out of the brw_compile struct...but fs_visitor
isn't going to have one of those in the future.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke 1f74002a98 i965/fs: Move brw_wm_compile::fp to fs_visitor.
Also change it from a brw_fragment_program to a gl_fragment_program,
since that seems to be what everything wants anyway.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke 7b0d30eb87 i965/fs: Remove struct brw_shader * parameter to fs_visitor constructor.
We can easily recover it from prog, and this makes it clear that we
aren't passing additional information in.

v2: Use an if-statement rather than the ?: operator (suggested by Eric).

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke a303df86de i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor.
Also, rather than having brw_wm_fs_emit poke at it directly, make it a
parameter to the fs_visitor constructor.

All other changes generated by search and replace (with occasional
whitespace fixup).

v2: Make dispatch_width const (as suggested by Paul); fix doxygen
    mistake (pointed out by Eric); update for rebase.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke 47a6a7b51b i965/fs: Move brw_wm_lookup_iz() to fs_visitor::setup_payload_gen4().
This necessitates compiling brw_wm_iz.c as C++.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke 2429c9d347 i965/fs: Move brw_wm_payload_setup() to fs_visitor::setup_payload_gen6()
Now that we only have the one backend, there's no real point in keeping
this separate.  Moving it should allow some future simplifications.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Kenneth Graunke ce96f6db90 i965/fs: Remove brw_wm_compile::computes_depth field.
Everybody determines this by checking if fp's OutputsWritten field
contains the FRAG_RESULT_DEPTH bit.  Rather than having payload setup
check this and set the computes_depth flag, we can just do the check in
the only place that actually used it: emit_fb_writes().

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-26 19:52:33 -08:00
Roland Scheidegger 529fe420ba gallivm: use the new mip per quad handling in texture fetch path
No longer have to split fetching into quads dynamically if mip levels
are not the same for all quads (aos sampling still always splits due
to performance reasons).
Instead handle multiple mip levels further down, minification etc. takes
this into account.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-11-27 03:30:55 +01:00
Roland Scheidegger 0b6554ba6f gallivm,llvmpipe: handle TXF (texelFetch) instruction, including offsets
This also adds some code to handle per-quad lods for more than 4-wide fetches,
because otherwise I'd have to integrate the texelFetch function into
the splitting stuff... (but it is not used yet outside texelFetch).
passes piglit fs-texelFetch-2D, fails fs-texelFetchOffset-2D due to I believe
a test error (results are undefined for out-of-bounds fetches, we return
whatever is at offset 0, whereas the test expects [0,0,0,1]).
Texel offsets are only handled by texelFetch for now, though the interface
can handle it for everything.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-11-27 03:26:49 +01:00
Chris Forbes 93c689a2df i965: Enable ARB_vertex_type_2_10_10_10_rev on Gen4+.
v2 (Kayden): Move the enable into an existing intel->gen >= 4 block
(as suggested by Ian).

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:48:29 -08:00
Chris Forbes 4a64efc01b i965: emit w/a for packed attribute formats in VS
Implements BGRA swizzle, sign recovery, and normalization
as required by ARB_vertex_type_10_10_10_2_rev.

V2: Ported to the new VS backend, since that's all that's left;
	fixed normalization.

V3: Moved fixups out of the GLSL-only path, so it works for FF/VP too.

V4 (Kayden): Rework ES3 normalization, don't heap allocate registers;
	tidy comments.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:35:10 -08:00
Chris Forbes 352ae51efd i965: set attribute w/a bits for packed formats
Flag the need for various workarounds to be applied by
the vertex shader.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:35:00 -08:00
Chris Forbes c3c680950d i965: Generalize GL_FIXED VS w/a support
Next few patches build on this to add other workarounds
for packed formats.

V2: rename BRW_ATTRIB_WA_COMPONENTS to BRW_ATTRIB_WA_COMPONENT_MASK;
V3 (Kayden): remove separate bit for ES3 signed normalization

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:34:28 -08:00
Chris Forbes 23f4411c41 i965: support 2_10_10_10 formats in get_surface_type.
Always use R10G10B10A2_UINT; Most of the other formats we'd like
don't actually work on the hardware. Will emit w/a for scaling,
sign recovery and BGRA swizzle in the VS.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:34:23 -08:00
Chris Forbes f9a08f7f0f i965: implement get_size for 2_10_10_10 formats
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 16:34:20 -08:00
Chris Forbes 894fe54ec9 i965/vs: add support for emitting SHL, SHR, ASR
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-26 14:02:30 -08:00
Matt Turner 8f3570efc7 mesa: Use correct glGetTransformFeedbackVarying name in error msg
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-11-26 10:08:05 -08:00
Andreas Boll 0f5e2ce854 build: use git ls-files for adding all Makefile.in into the release tarball
Until we have proper 'make dist' this is an improvement of the current
situation, because each time some old Makefiles got converted to automake
we had to update the tarballs target.

NOTE: This is a candidate for the 9.0 branch.

Cc: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
2012-11-26 19:03:21 +01:00
Eric Anholt 97747ac88f i965: Fix hangs with FP KIL instructions pre-gen6.
We can't support IF statements in 16-wide on these.  To get back to 16-wide
for these shaders, we need to support predicate on discard instructions in the
backend IR, which is something we've sort of got on the list to do anyway.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55828
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-25 20:22:02 -08:00
Eric Anholt 59bfd66a61 i965/gen4: Fix memory leak each time compile_gs_prog() is called.
Commit 774fb90db3 introduced a ralloc context to
each user of struct brw_compile, but for this one a NULL context was used,
causing the later ralloc_free(mem_ctx) to not do anything.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55175
NOTE: This is a candidate for the stable branches.
2012-11-25 18:25:26 -08:00
Eric Anholt 244db0855c i965/gen4: Fix LOD bias texturing since my fixed reg classes change.
We have a special case where non-shadow comparison with LOD requires using a
SIMD16 vec4 in an 8-wide shader, which appears in the register allocator as a
size 8 vgrf.

Fixes assertions in various piglit tests and webgl conformance.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56521
2012-11-25 18:25:26 -08:00
Marek Olšák cff4c948ed r600g: fix broken streamout if streamout_begin caused a context flush
This fixes graphics corruption in the case where the DISCARD_RANGE flag
is used to map a buffer.

NOTE: This is a candidate for the stable branches.
2012-11-23 00:42:02 +01:00
Marek Olšák d172fa825b r600g: fix ARB_map_buffer_alignment with unaligned offsets and staging buffers 2012-11-22 22:40:06 +01:00
Vinson Lee f884005771 scons: Append x11 library path if linking x11 library.
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2012-11-21 22:34:20 -08:00
Kenneth Graunke bf75a1f092 mesa/vbo: Fix scaling issue in 2-bit signed normalized packing.
Since a signed 2-bit integer can only represent -1, 0, or 1, it is
tempting to simply to convert it directly to a float.  This maps it
onto the correct range of [-1.0, 1.0].  However, it gives different
values compared to the usual equation:

(2.0 *  1.0 + 1.0) * (1.0 / 3.0) = +1.0           (same)
(2.0 *  0.0 + 1.0) * (1.0 / 3.0) = +0.33333333... (different)
(2.0 * -1.0 + 1.0) * (1.0 / 3.0) = -0.33333333... (different)

According to the GL_ARB_vertex_type_2_10_10_10_rev extension, signed
normalization is performed using equation 2.2 from the GL 3.2
specification, which is:

   f = (2c + 1)/(2^b - 1).                                (2.2)

Comments below that equation state: "In general, this representation is
used for signed normalized fixed-point parameters in GL commands, such
as vertex attribute values."  Which is what we're doing here.

The 3.2 specification goes on to declare an alternate formula:

   f = max{c/(2^(b-1) - 1), -1.0}                         (2.3)

which is closer to the existing code, and maps the end points to exactly
-1.0 and 1.0.  Comments below the equation state: "In general, this
representation is used for signed normalized fixed-point texture or
framebuffer values."  Which is *not* what we're doing here.

It then states: "Everywhere that signed normalized fixed-point
values are converted, the equation used is specified."  This is the real
clincher: the extension explicitly specifies that we must use equation
2.2, not 2.3.  So we need to do (2x + 1) / 3.

This matches the behavior expected by oglconform's packed-vertex test,
and is correct for desktop GL (pre-4.2).  It's not correct for ES 3.0,
but a future patch will correct that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marek Olšák <maraeo@gmail.com>
2012-11-21 20:32:54 -08:00
Kenneth Graunke e9967aba61 mesa/vbo: Fix scaling issue in 10-bit signed normalized packing.
For the 10-bit components, the divisor was incorrect.  A 10-bit signed
integer can represent -2^9 through 2^9 - 1, which leads to the following
ranges:

       (float)value.x          -> [ -512,  511]
2.0F * (float)value.x          -> [-1024, 1022]
2.0F * (float)value.x + 1.0F   -> [-1023, 1023]

So dividing by 511 would incorrectly scale it to approximately:
[-2.001956947, 2.001956947].  To correctly scale to [-1.0, 1.0], we need
to divide by 1023.

This correctly implements the desktop GL rules.  ES 3.0 has different
rules, but those will be implemented in a separate patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marek Olšák <maraeo@gmail.com>
2012-11-21 20:29:38 -08:00
Alex Deucher e2df37f69a radeonsi: add a new SI pci id
Note: this is a candidate for the stable branch.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-11-21 18:49:00 -05:00
Vinson Lee 10f214e5b2 i915: Fix wrong sizeof argument in i915_update_tex_unit.
The bug was found by Coverity.

NOTE: This is a candidate for the stable branches.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-11-21 15:02:35 -08:00
Andreas Boll 59b3d3ad6e Add .dirstamp to toplevel .gitignore 2012-11-21 18:25:10 +01:00
Andreas Boll f7e2e864c8 gallium/tests: update .gitignore files 2012-11-21 18:24:30 +01:00
Eric Anholt d82b873a50 i965/fs: Add helper functions for IF and CMP and use them.
v2: Rebase on gen6-if fix.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2012-11-20 13:38:38 -08:00
Eric Anholt 32d6809bb5 i965/fs: Add helper functions for generating ALU ops, like in the VS.
This gives us checking of our arguments (no more passing 1 operand to
BRW_OPCODE_MUL!), at the cost of a couple of extra parens.

v2: Rebase on gen6-if fix.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
2012-11-20 12:55:08 -08:00
Eric Anholt 1665af3066 i965/gen4: Fix crash with fragment programs and texture rectangle.
This was a regression in the brw_fs_fp.cpp change.  We just need to return
something good enough to get the IR generation to the end without crashing,
but ir->type isn't initialized and we wanted something of the coordinate's
type anyway.

Fixes around 30 piglit cases on my ilk system in drawpixels and framebuffer
blit.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56962
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-19 22:33:44 -08:00
Eric Anholt d411bbd5bd i965: Disable the GB clip test when a limited viewport is set.
The theory of the guardband is that you extend the clip volume to avoid
expensive clipping computation, and just let fragments outside the viewport
get clipped by the drawable's bounds.  But if a smaller-than-window-size
viewport is set, and we don't also happen to have a scissor set, then
rendering could incorrectly extend outside of the viewport when it should have
been clipped to the viewport.

Fixes the new piglit triangle-guardband-viewport test.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 9.0 branch.
2012-11-19 22:33:44 -08:00
Eric Anholt 23e7b81f2d i965: Use fewer temporary variables in clip setup.
When you're comparing to the spec, you're trying to immediately see what
numbered dword of the packet your bit ends up in.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NOTE: This is a candidate for the 9.0 branch.
2012-11-19 22:33:43 -08:00
Eric Anholt afc5a26b5c Revert "i965/fs: Fix conversions float->bool, int->bool"
This reverts commit cf0bbb30f6.  It
was just papering over the bug fixed in the previous commit.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-19 22:33:43 -08:00
Eric Anholt 0482998ccc i965/fs: Fix the gen6-specific if handling for 80ecb8f15b
Fixes oglconform shad-compiler advanced.TestLessThani.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48629
NOTE: This is a candidate for the 9.0 branch.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-11-19 22:33:43 -08:00
Chad Versace c9f5126b15 intel: Use designated initializers for DRI extension structs
All Intel code is compiled with -std=c99. There is no excuse to not use
designated initializers.

As a nice benefit, the code is now more friendly to grep. Without
designated initializers, psychic prowess is required to find the
initialization of DRI extension function pointers with grep.  I have
observed several people, when they first encounter the DRI code, fail at
statically chasing the DRI function pointers due to this problem.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:09:55 -08:00
Chad Versace 62332f4125 dri: Use designated initializers for DRI extension structs
The dri directory is compiled with -std=c99. There is no excuse to not use
designated initializers.

As a nice benefit, the code is now more friendly to grep. Without
designated initializers, psychic prowess is required to find the
initialization of DRI extension function pointers with grep.  I have
observed several people, when they first encounter the DRI code, fail at
statically chasing the DRI function pointers due to this problem.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:09:55 -08:00
Eric Anholt fdd6d146d9 i965: Use the separate stencil buffer's offsets for stencil setup.
For a packed depth/stencil buffer on separate stencil hardware, the
separate depth miptree is set up with alignment of 4,4 and the separate
stencil miptree is setup with alignment of 8,8.  We can't just use the
irb->draw_{x,y} offsets for stencil, since that is the offset in the
depth miptree.

Fixes 12 piglit depthstencil testcases on ivb.

Acked-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt 52ee1a7269 i965: Move all the depth/stencil/hiz offset logic into the workaround.
Given that we have the mask information here (assuming the rebase is to
the same tiling, which is safe), we can just save a set of miptrees and
offsets and the global intra-tile offset in the context and cut out a
bunch of logic.  This will also save emitting the next fix I need to do
twice.

Acked-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt 9ec6a54ba9 i965: When rebasing depth or stencil, update x/y before deciding the other.
Fixes a theoretical problem where we had an aligned depth buffer and a
misaligned stencil buffer with a matching tile offset, so we would fail
to rebase depth even after the needed tile offset changed due to the
rebase of stencil.

It should also fix double-rebase of a misaligned packed depth/stencil
renderbuffer, which may have been a performance issue.

Acked-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt be9e664307 intel: Push face/level -> slice handling to the caller of get_image_offset().
We were always passing 0 for one of the two fields, and the code just used
whichever one wasn't 0.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt c1fabea1c5 i965: Add some checks for array textures in unsupported paths.
I noticed these in the next patch where these paths were using the Face
of a teximage but didn't have array handling.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt 923c4b3f4a i965: Add a little bit more debug info for validate blits.
The kind of data you're copying is definitely an interesting variable.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt e5671040c5 intel: Remove dead function prototype.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Eric Anholt 1f35ec585f i965: Remove stale comment about wrapped_depth.
I removed that code almost a year ago.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-11-19 15:07:22 -08:00
Kenneth Graunke 1f74a5b3cc mesa: Mark GetBufferParameteri64v as implemented.
Apparently this was accidentally marked as unimplemented, and thus not
put in the dispatch table.

Fixes 7 es3conform tests:
- copy_buffer_parameters
- copy_buffer_data
- copy_buffer_usage
- pixel_buffer_object_bind
- pixel_buffer_object_parameteriv
- pixel_buffer_object_texture_read
- pixel_buffer_object_usage

v2: Also update the DispatchSanity test for this change.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-11-19 11:49:04 -08:00