Commit Graph

691 Commits

Author SHA1 Message Date
Samuel Pitoiset a00be79d80 radv: remove small overhead of radv_pipeline_has_ngg()
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4784
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
2021-05-24 08:50:47 +00:00
Bas Nieuwenhuizen 733c9b6d17 radv: Add RT pipeline bind.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen eba2b4137e radv: Add support for RT bind point.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
2021-05-18 18:29:36 +00:00
Rhys Perry 157c6b0f33 radv,aco: use per-attribute vertex descriptors for robustness
We have to use a different num_records for each attribute to correctly
implement robust buffer access.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 60059 (41.06% of 146267) affected shaders:
VGPRs: 2169040 -> 2169024 (-0.00%); split: -0.02%, +0.02%
CodeSize: 79473128 -> 81156016 (+2.12%); split: -0.00%, +2.12%
MaxWaves: 1635360 -> 1635258 (-0.01%); split: +0.00%, -0.01%
Instrs: 15559040 -> 15793205 (+1.51%); split: -0.01%, +1.52%
Latency: 90954792 -> 91308768 (+0.39%); split: -0.30%, +0.69%
InvThroughput: 14937873 -> 14958761 (+0.14%); split: -0.04%, +0.18%
VClause: 444280 -> 412074 (-7.25%); split: -9.22%, +1.97%
SClause: 588545 -> 644141 (+9.45%); split: -0.54%, +9.99%
Copies: 1010395 -> 1011232 (+0.08%); split: -0.44%, +0.53%
Branches: 274279 -> 274282 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1431171 -> 1405056 (-1.82%); split: -2.89%, +1.07%
PreVGPRs: 1575253 -> 1575259 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
2021-05-10 12:09:14 +00:00
Samuel Pitoiset 54b0cfb061 radv: fix extending the dirty bits to 64-bit
New dynamic states added for VK_EXT_extended_dynamic_state2 causes
GPU hangs with vkd3d-proton.

Fixes: 7bdd569d7e ("radv: extend the dirty bits to 64-bit")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10693>
2021-05-07 18:09:00 +00:00
Samuel Pitoiset dd19bf9d7d radv: implement dynamic rasterizer discard enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:59 +00:00
Samuel Pitoiset c40d7fadc3 radv: implement dynamic primitive restart enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:59 +00:00
Samuel Pitoiset f2933e9872 radv: implement dynamic depth bias enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:58 +00:00
Samuel Pitoiset 44e7bcf942 radv: declare new dynamic states for VK_EXT_extended_dynamic_state2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:58 +00:00
Samuel Pitoiset 33ede796d5 radv: fix missing ITERATE_256 for D/S MSAA images that are TC-compat HTILE
To make them readable by shaders, only needed on GFX10+.

This also fixes corruption with Control and MSAA.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10610>
2021-05-06 06:30:05 +00:00
Samuel Pitoiset d21ffa9c7d radv: add the provoking vertex mode to the pipeline/shader keys
It might change the NGG code on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10449>
2021-04-27 07:31:02 +00:00
Samuel Pitoiset 9a0098ee50 radv: cleanup LLVM related includes
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10403>
2021-04-23 11:52:01 +02:00
Samuel Pitoiset 6aaa325f89 radv: remove radv_image_iview::multiplane_planes
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10218>
2021-04-20 12:16:33 +00:00
Samuel Pitoiset 8198aeac8d radv: remove radv_image_iview::bo
This saves one 64-bit pointer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10218>
2021-04-20 12:16:33 +00:00
Rhys Perry 86d903e88d radv: fix clearing DCC-compressed e5b9g9r9 images
Fixes
dEQP-VK.api.image_clearing.core.clear_color_image.2d.optimal.single_layer.e5b9g9r9_ufloat_pack32_33x128
with RADV_DEBUG=forcecompress on GFX10.3.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10176>
2021-04-16 11:56:32 +01:00
Rhys Perry ec70882238 radv: fix barrier in radv_decompress_dcc_compute shader
ACO doesn't create a waitcnt for barriers between texture samples and
image stores because texture samples are supposed to use read-only
memory. It could also schedule the barrier to above the texture sample.
We also have use a larger memory scope to avoid an ACO optimization.

Tested on GFX8 with Sachsa Willems deferred sample. With some DCC
decompressions and the compute path forced.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 21.1 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9496>
2021-04-15 12:02:36 +00:00
Samuel Pitoiset 0b7e346203 radv: add support for copying VRS rates into HTILE
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset 513a166a7b radv: handle the VRS attachment subpass
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset bb88f73ad3 radv: create an image for VRS if no depth/stencil attachment is bound
The Vulkan spec doesn't require the application to always binds
a depth/stencil attachment when a VRS attachment is used inside the
same subpass.

To handle this situation, the driver creates a global 4096x4096
VRS image that will be bind at draw-time if needed. This isn't
super ideal but we have to do that unfortunately.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset 7bd3a9f502 radv: update the HTILE clear word when VRS is used
SR1 is the VRS x-rate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset d075711b0e radv: do not use the whole HTILE buffer for depth when VRS is used
The stencil data needs to be included for storing the VRS rates
into the HTILE buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset 73dac68cb8 radv: configure the VRS HTILE encoding size
Any depth buffer can potentially use VRS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset 62033e0cb3 radv: determine if attachment VRS is enabled
When VRS attachment, any depth buffer can potentially be used for VRS.
We also have to create a global depth buffer if the app doesn't
provide one.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Marek Olšák 7e68fae25f ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.

The RADV code is disabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
2021-04-13 03:17:42 +00:00
Marek Olšák 468836317b ac/surface: unify htile_* and dcc_* fields as meta_* fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Bas Nieuwenhuizen 59c501ca35 radv: Format.
Using

find ./src/amd/vulkan -regex '.*/.*\.\(c\|h\|cpp\)' | xargs -P8 -n1 clang-format --style=file -i

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10091>
2021-04-10 03:31:58 +02:00
Samuel Pitoiset 1ad295ed6f radv: allow to force VRS rates on GFX10.3 with RADV_FORCE_VRS
This allows to force the VRS rates via RADV_FORCE_VRS, the supported
values are 2x2, 1x2 and 2x1. This supports the primitive shading rate
mode for non GUI elements.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7794>
2021-04-09 14:47:53 +02:00
Samuel Pitoiset b4a66b29cd radv: add MSAA support to CopyImage() on compute queue
CopyImage supports copying MSAA images if the number of samples match.
Found by inspection because this is untested by CTS for some reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10055>
2021-04-09 07:05:24 +00:00
Bas Nieuwenhuizen 6ff88a823b radv: Add retiling for foreign queues.
This way modifier images that don't go through the present layout
get the retile executed properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Bas Nieuwenhuizen dece117fdc radv: Support DCC without DCC/FCE predicates.
Imported images can't have this as part of the associated memory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Bas Nieuwenhuizen b61efd53b4 radv: Support DCC without a fast clear value.
For imported images we can't have one in the associated memory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Samuel Pitoiset 63772f3ca5 radv: add MSAA support to ClearColorImage() on compute queue
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10070>
2021-04-08 17:42:15 +00:00
Chad Versace 5e6db19168 anv: Remove vkCreateDmaBufINTEL (v4)
Superceded by VK_EXT_image_drm_format_modifier.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1466>
2021-04-08 14:15:55 +00:00
Samuel Pitoiset 8b80e8f832 radv: init CMASK/FMASK/DCC in parallel
To remove bubbles during layout transitions from UNDEFINED, especially
with MSAA because we might have all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10004>
2021-04-05 16:21:12 +00:00
Samuel Pitoiset 14b312b223 radv: handle implicit subpass dependencies per attachment
From the Vulkan spec 1.2.172:

"If there is no subpass dependency from VK_SUBPASS_EXTERNAL to the
 first subpass that uses an attachment, then an implicit subpass
 dependency exists from VK_SUBPASS_EXTERNAL to the first subpass
 it is used in."

"Similarly, if there is no subpass dependency from the last subpass
 that uses an attachment to VK_SUBPASS_EXTERNAL, then an implicit
 subpass dependency exists from the last subpass it is used in to
 VK_SUBPASS_EXTERNAL."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9714>
2021-04-05 11:42:51 +00:00
Alyssa Rosenzweig 06ebbde630 vulkan: Deduplicate mesa stage conversion
Across every driver...

v2: Add casts to appease -fpermissive used on CI.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9477>
2021-04-03 17:34:39 +00:00
Samuel Pitoiset 87c8764448 radv: compress FMASK for all layouts except GENERAL
The COMPRESSION bit is FMASK and this is much faster! Should
speedup transfer dst operations with MSAA images considerably.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9990>
2021-04-02 06:34:45 +00:00
Mike Blumenkrantz df1c45890d radv: don't emit baseinstance and drawid if neither is used
indirect draw dispatch contributed by Samuel Pitoiset <samuel.pitoiset@gmail.com>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz 0a8b091922 radv: track whether baseinstance is used on the pipeline struct
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz b1b867033e radv: track whether drawid is used on the pipeline struct
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Samuel Pitoiset 1df4f11eb5 radv: require DRM 3.35+
Linux Kernel 4.15+ is now required for RADV, this kernel has been
released 3 years ago and should be in most modern distros.

This allows us to remove a lot of legacy code for fence/semaphore.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9800>
2021-03-29 19:48:19 +00:00
Bas Nieuwenhuizen a7c0cf500b radv: Enable DCC for image stores on GFX10.
Since image stores can now compress and we can't track image stores
this also stops using predication for DCC decompression.

In GFX10 this was benchmarked to be faster. For GFX10.3 the microbenchmarks
are not as possible though I haven't tested any games, so this is not enabled
there yet.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6796>
2021-03-26 16:16:24 +00:00
Samuel Pitoiset b2c1ed262d radv: restore previous MRT CB_SHADER_MASK logic
It was moved to the shader info pass to compute MRTs from the shader
outputs to fix some CTS failures but this is actually unnecessary.
The CTS failures were actually CTS bugs.

This reverts 70cc80805c ("radv: compute CB_SHADER_MASK from the
fragment shader outputs") and 76ee45d3a8 ("radv: adjust CB_SHADER_MASK
for dual-source blending in the shader info pass").

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9703>
2021-03-22 11:32:49 +00:00
Samuel Pitoiset 7bdd569d7e radv: extend the dirty bits to 64-bit
For future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9603>
2021-03-17 09:21:38 +00:00
Mike Blumenkrantz 1d1c7a965c radv: use common interfaces for shader modules
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9508>
2021-03-15 21:47:44 +00:00
Samuel Pitoiset 15fc0c351a radv: fix potential clears with non renderable images on GFX9+
Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9474>
2021-03-12 16:09:42 +00:00
Jason Ekstrand 4fb6c051c9 anv: Move vk_format helpers to common code
The Android ones we put in anv_android.c.  Maybe one day we'll want a
vk_android.h to put some common Android stuff but, for now, let's keep
it contained to ANV's android code.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8857>
2021-03-10 18:17:31 +00:00
Rhys Perry 9f8a0b797e radv: cache pipeline statistics
Applications rarely require them, but this improves fossil-db replay time.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9411>
2021-03-05 17:01:16 +00:00
Rhys Perry 21697082ec radv: don't shrink image stores for The Surge 2
The game seems to declare the wrong format.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e4d75c22 ("nir/opt_shrink_vectors: shrink image stores using the format")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4347
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9229>
2021-03-03 14:18:37 +00:00
Samuel Pitoiset 8a47422d97 radv: do not scale the depth bias for D16_UNORM depth surfaces
Scaling the depth bias doesn't seem correct with Vulkan. This is
probably the root cause of the shadow artifacts differences between
RADV and AMDVLK/AMDGPU-PRO.

Fix dEQP-VK.rasterization.depth_bias.d16_unorm.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2217
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9249>
2021-02-25 08:17:27 +01:00