Commit Graph

766 Commits

Author SHA1 Message Date
Samuel Pitoiset a00be79d80 radv: remove small overhead of radv_pipeline_has_ngg()
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4784
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10908>
2021-05-24 08:50:47 +00:00
Samuel Pitoiset 726cb2d6f6 ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10911>
2021-05-21 19:46:56 +00:00
Timur Kristóf 2bb1bf78f0 radv/cmd_buffer: Fix warning by initializing instance count.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
2021-05-20 17:11:22 +00:00
Samuel Pitoiset b1171e5ffe Revert "radv: Do not access set layout during vkCmdBindDescriptorSets."
This was a temporary workaround for a Baldur's Gate 3 bug which
should now be fixed.

This reverts commit eb104e949e.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3701
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10839>
2021-05-20 13:38:33 +00:00
Bas Nieuwenhuizen 07e0aab9d9 radv: Implement vkCmdTraceRays.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen 733c9b6d17 radv: Add RT pipeline bind.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
2021-05-18 18:29:36 +00:00
Bas Nieuwenhuizen eba2b4137e radv: Add support for RT bind point.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9767>
2021-05-18 18:29:36 +00:00
Samuel Pitoiset 143c7f0375 radv: add missing entrypoints for VK_EXT_extended_dynamic_state2
Fixes warnings with dEQP-VK.api.version_check.entry_points.

Fixes: d96507b73f ("radv: advertise VK_EXT_extended_dynamic_state2")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10831>
2021-05-18 09:32:37 +00:00
Rhys Perry a54f111831 radv,aco: compact vertex buffer descriptors
It seems common for there to be holes.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 33791 (23.10% of 146267) affected shaders:
(no statistics changed)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
2021-05-10 12:09:14 +00:00
Rhys Perry 157c6b0f33 radv,aco: use per-attribute vertex descriptors for robustness
We have to use a different num_records for each attribute to correctly
implement robust buffer access.

fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 60059 (41.06% of 146267) affected shaders:
VGPRs: 2169040 -> 2169024 (-0.00%); split: -0.02%, +0.02%
CodeSize: 79473128 -> 81156016 (+2.12%); split: -0.00%, +2.12%
MaxWaves: 1635360 -> 1635258 (-0.01%); split: +0.00%, -0.01%
Instrs: 15559040 -> 15793205 (+1.51%); split: -0.01%, +1.52%
Latency: 90954792 -> 91308768 (+0.39%); split: -0.30%, +0.69%
InvThroughput: 14937873 -> 14958761 (+0.14%); split: -0.04%, +0.18%
VClause: 444280 -> 412074 (-7.25%); split: -9.22%, +1.97%
SClause: 588545 -> 644141 (+9.45%); split: -0.54%, +9.99%
Copies: 1010395 -> 1011232 (+0.08%); split: -0.44%, +0.53%
Branches: 274279 -> 274282 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1431171 -> 1405056 (-1.82%); split: -2.89%, +1.07%
PreVGPRs: 1575253 -> 1575259 (+0.00%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
2021-05-10 12:09:14 +00:00
Samuel Pitoiset 54b0cfb061 radv: fix extending the dirty bits to 64-bit
New dynamic states added for VK_EXT_extended_dynamic_state2 causes
GPU hangs with vkd3d-proton.

Fixes: 7bdd569d7e ("radv: extend the dirty bits to 64-bit")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10693>
2021-05-07 18:09:00 +00:00
Samuel Pitoiset dd19bf9d7d radv: implement dynamic rasterizer discard enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:59 +00:00
Samuel Pitoiset c40d7fadc3 radv: implement dynamic primitive restart enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:59 +00:00
Samuel Pitoiset f2933e9872 radv: implement dynamic depth bias enable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10340>
2021-05-06 20:58:58 +00:00
Samuel Pitoiset a854a9fa62 radv: fix various CMASK regressions on GFX9
This fixes a bunch of MSAA related CTS regressions. This restores
previous behaviour on GFX9 but it should be fixed properly.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10374>
2021-04-27 06:51:26 +00:00
Samuel Pitoiset 3d979c9169 radv: make sure CP DMA is idle before executing secondary command buffers
Buffer copies with CP DMA aren't synced.

Fix dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.65536
flakes on GFX10+.

Fixes: e870796113 ("radv: prefer CP DMA for GTT buffer copies/clears on dGPUs due to slow PCIe")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10427>
2021-04-23 13:45:24 +02:00
Samuel Pitoiset a12b844d40 radv: fix emitting default depth bounds state on GFX6
GFX6 has no CLEAR_STATE.

One step towards Vulkan conformance on these old chips.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10347>
2021-04-23 08:37:11 +02:00
Samuel Pitoiset 8198aeac8d radv: remove radv_image_iview::bo
This saves one 64-bit pointer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10218>
2021-04-20 12:16:33 +00:00
Samuel Pitoiset 1d3542694b radv: fix emitting depth bias when beginning a command buffer
If depth bias is enabled but zero values used, they were never
emitted to the command buffer because they are equal to the default
values.

Previously, they were always emitted when the bound DS attachment
changed.

This should fix some sort of Z fighting with Dota2 on all GPUs.
This also fixes a different issue (ie. some occlusion queries failures)
on GFX6 because CLEAR_STATE is not used on that chip.

Fixes: 8a47422d97 ("radv: do not scale the depth bias for D16_UNORM depth surfaces")
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10310>
2021-04-20 09:09:38 +00:00
Marek Olšák ec1ddb976a amd/registers: rename IMG_FORMAT to GFX10_FORMAT to disambiguate the meaning
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10261>
2021-04-17 02:37:49 +00:00
Bas Nieuwenhuizen 057ec395a4 radv: Refactor cs_domain to be a winsys function.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10198>
2021-04-14 15:16:17 +00:00
Samuel Pitoiset ee77dde396 radv: configure the VRS combiners when an attachment is used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset ea370f45b4 radv: copy VRS rates to HTILE when beginning a subpass
The global VRS image is created on-demand to avoid wasting space.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Samuel Pitoiset 164b1884c0 radv: bind our internal depth buffer when not provided by the app
When a subpass uses a VRS attachment without binding a depth/stencil
attachment (yes, this is allowed by the Vulkan spec), we have to bind
our internal depth buffer that contains the VRS data.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10187>
2021-04-14 09:31:13 +00:00
Bas Nieuwenhuizen 61a1a385d3 radv: Re-enable retiling.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10037>
2021-04-13 12:08:24 +00:00
Marek Olšák 7e68fae25f ac,radeonsi: rewrite DCC retiling without the DCC retile map
The retile map is removed and replaced by direct DCC address computations
in the retile shader using the new function ac_nir_dcc_addr_from_coord.

The RADV code is disabled.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10003>
2021-04-13 03:17:42 +00:00
Marek Olšák faf10bd49d ac/surface: use named "color and "zs" structures in unions
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Marek Olšák 468836317b ac/surface: unify htile_* and dcc_* fields as meta_* fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Marek Olšák 2fd8018845 ac/surface: split dcc level info from surface_info to save space
stencil level info doesn't have DCC

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12 20:53:45 +00:00
Bas Nieuwenhuizen 59c501ca35 radv: Format.
Using

find ./src/amd/vulkan -regex '.*/.*\.\(c\|h\|cpp\)' | xargs -P8 -n1 clang-format --style=file -i

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10091>
2021-04-10 03:31:58 +02:00
Bas Nieuwenhuizen 6ff88a823b radv: Add retiling for foreign queues.
This way modifier images that don't go through the present layout
get the retile executed properly.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Bas Nieuwenhuizen dece117fdc radv: Support DCC without DCC/FCE predicates.
Imported images can't have this as part of the associated memory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Bas Nieuwenhuizen b61efd53b4 radv: Support DCC without a fast clear value.
For imported images we can't have one in the associated memory.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9998>
2021-04-08 22:29:12 +00:00
Samuel Pitoiset f280367a27 radv: perform MSAA color decompression for storage images with DCC
For MSAA storage images with DCC, we also need to perform a MSAA
color decompression.

Fixes dEQP-VK.pipeline.multisample.storage_image.* if DCC stores
is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9854>
2021-04-07 15:35:07 +00:00
Samuel Pitoiset 8b80e8f832 radv: init CMASK/FMASK/DCC in parallel
To remove bubbles during layout transitions from UNDEFINED, especially
with MSAA because we might have all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10004>
2021-04-05 16:21:12 +00:00
Marek Olšák b3e7c77f13 amd: fix parsing the last dword of DMA_DATA packets
It was parsing it as SQ_WAVE_GPR_ALLOC instead of COMMAND.
Change the offset to an odd number to work around it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Samuel Pitoiset 57916fbdcd radv: use COLOR_ATTACHMENT_OPTIMAL for fast clear/hw resolve operations
This should be equivalent without needed to force enable FMASK for
some specific internal pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9940>
2021-04-02 08:36:19 +02:00
Samuel Pitoiset fc2186d302 radv: do not force enable FMASK during MSAA blits
This is no longer needed since FMASK is also compressed for
transfer dst operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9940>
2021-04-02 08:36:16 +02:00
Samuel Pitoiset 6dbf975cb9 radv: cleanup FMASK expand transitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9990>
2021-04-02 06:34:45 +00:00
Samuel Pitoiset 87c8764448 radv: compress FMASK for all layouts except GENERAL
The COMPRESSION bit is FMASK and this is much faster! Should
speedup transfer dst operations with MSAA images considerably.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9990>
2021-04-02 06:34:45 +00:00
Mike Blumenkrantz 71e39c79fd radv: don't reset vertex state params on pipeline bind if reg layout matches
this is unnecessary since the locations will match

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz df1c45890d radv: don't emit baseinstance and drawid if neither is used
indirect draw dispatch contributed by Samuel Pitoiset <samuel.pitoiset@gmail.com>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz d67c1bc74d radv: reorder vertex shader params
put baseinstance last since it's the least updated

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz 4e0a3c2527 radv: break out vertex shader param emission into separate function
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz b1b867033e radv: track whether drawid is used on the pipeline struct
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz 75a2476dfb radv: refactor draw dispatch
this breaks up the monolithic draw path used for all draw calls into
pre/post functions to handle general setup and a couple helper functions
to more directly handle different draw modes in a way that's both more readable
and, potentially, more optimizable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Mike Blumenkrantz d0ef28d85e radv: stop zeroing radv_draw_info during draw
this is a big struct, and there's only a couple extra members that need
to be initialized to hit the right codepaths

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8788>
2021-03-31 13:54:24 +00:00
Bas Nieuwenhuizen a7c0cf500b radv: Enable DCC for image stores on GFX10.
Since image stores can now compress and we can't track image stores
this also stops using predication for DCC decompression.

In GFX10 this was benchmarked to be faster. For GFX10.3 the microbenchmarks
are not as possible though I haven't tested any games, so this is not enabled
there yet.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6796>
2021-03-26 16:16:24 +00:00
Samuel Pitoiset 5cb6999bc3 radv: use common entrypoints for VK_KHR_create_renderpass2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9601>
2021-03-24 11:21:53 +00:00
Tony Wasserka 2fb71504f0 radv: Skip 0-sized index buffers only when necessary
This workaround is only needed on Navi10 and Navi14.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9429>
2021-03-22 11:47:25 +01:00