Commit Graph

6449 Commits

Author SHA1 Message Date
Anuj Phogat 99331f6deb intel: Rename genx10 field in gen_device_info struct to verx10
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)genx10" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)genx10/info\1\2verx10/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat cc422fa498 intel: Rename ISL_DEV_GEN to ISL_GFX_VER
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "ISL_DEV_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/ISL_DEV_GEN/ISL_GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat 9da8a55b08 intel: Rename GEN_GEN macro to GFX_VER
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_GEN" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_GEN/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Anuj Phogat 295bb3c263 intel: Rename GEN_VERSIONx10 macro to GFX_VERx10
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN_VERSION" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN_VERSION/GFX_VER/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:06 +00:00
Jason Ekstrand d5b56debde anv: Implement VK_EXT_conservative_rasterization
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4480
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9960>
2021-04-01 13:34:55 +00:00
Lionel Landwerlin 200e56f84d intel/fs: implement another copy propagation restriction
We are missing an additional restriction on CHV & upcoming Xe-Hp.

v2: Quote BSW PRMs (Curro)
    Check source is not a scalar (Curro)
    Fix comment (Marcin)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9929>
2021-04-01 07:48:06 +00:00
Lionel Landwerlin aa53665fda intel/fs/copy_prop: check stride constraints with actual final type
In some cases we will change the type of the destination register of
an instruction. This is the type we should use to verify that we're
allow to do the replacement.

Otherwise we can hit restrictions on CHV and upcoming Xe-Hp for
instance where the copy propagation transforms this :

send(16) (mlen: 2) vgrf10:UD, 0u, 0u, vgrf35:D, null:UD
mov(16) vgrf11:UW, vgrf10<2>:UW
mov(16) vgrf12:UW, vgrf10+0.2<2>:UW
mov(16) vgrf15:HF, |vgrf11|:HF
mov(16) vgrf16:HF, |vgrf12|:HF
mov(8) vgrf41<2>:UW, vgrf15+0.0:UW group0
mov(8) vgrf42<2>:UW, vgrf15+0.16:UW group8
mov(8) vgrf45<2>:UW, vgrf16+0.0:UW group0
mov(8) vgrf46<2>:UW, vgrf16+0.16:UW group8

into this :

send(16) (mlen: 2) vgrf10:UD, 0u, 0u, vgrf35:D, null:UD
mov(8) vgrf41<2>:HF, |vgrf10+0.0|<2>:HF group0
mov(8) vgrf42<2>:HF, |vgrf10+1.0|<2>:HF group8
mov(8) vgrf45<2>:HF, |vgrf10+0.2|<2>:HF group0
mov(8) vgrf46<2>:HF, |vgrf10+1.2|<2>:HF group8

Because of the floating point use, stride and offets should be the
same.

v2: Fix final destination type selection (Curro)

v3: constify (Curro)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9832>
2021-03-29 22:14:45 +00:00
Kenneth Graunke d67b343aa0 intel: Mark an otherwise unused variable in intel_dump_gpu as ASSERTED
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9862>
2021-03-29 20:02:09 +00:00
Tapani Pälli 10cdfce14e intel/common: disable batch decoder on Android platform
when building with Meson. It requires libexpat that is not available
on Android and we want to avoid it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9848>
2021-03-27 19:26:22 +02:00
Lionel Landwerlin 6d72f404df intel/nullhw: fix build
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4507
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9849>
2021-03-26 20:12:40 +00:00
Iván Briano 042d24971e anv: use helper function to get the buffer size
This ensures we get a properly aligned size for the buffer so we don't
trip over HW limits for push constants.

Closes #3703
Fixes dEQP-VK.robustness.image_robustness.push.* on HSW

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>
2021-03-25 15:22:20 -07:00
Iván Briano 54b848b245 anv: move buffer size alignment into helper function
And use ANV_UBO_ALIGNMENT for it instead of a magic number.
This increases the alignment to 64B, but that ought to be good for
everyone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9699>
2021-03-25 15:20:53 -07:00
Lionel Landwerlin 8b586d9ed6 intel: Add null hw layer
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2832>
2021-03-25 19:10:03 +00:00
Jason Ekstrand 82b25a1d75 anv: Align inline uniform data to ANV_UBO_ALIGNMENT
If we're going to have a #define for UBO alignments, it's probably a
good idea to make sure everything is aligned to that.  This increases
the alignment from 32B to 64B but that shouldn't hurt anyone.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9837>
2021-03-25 19:01:24 +00:00
Kenneth Graunke 5ae276f7e0 intel: Fix release build breakage
We missed changing one instance of debug_flag to debug_enabled in a
release-only ifdef branch.

Fixes: 758eb18c6f ("intel/compiler: Make vec4 generator take debug_enabled as a parameter")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9839>
2021-03-25 11:36:58 -07:00
Danylo Piliaiev 2bff8fd53b nir: add nir_shader_as_str function
It would be later used by Turnip in implementation of
VK_KHR_pipeline_executable_properties.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8877>
2021-03-25 13:53:33 +00:00
Tapani Pälli 382e5f2737 anv/android: fix image creation with external format
This fixes crashes seen with following group of tests:
   android.graphics.cts.BasicVulkanGpuTest

Fixes: 6fa56273be ("anv/image: Drop duplicate 'format' in anv_image_create()")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9799>
2021-03-25 07:33:38 +02:00
Caio Marcelo de Oliveira Filho e93c8ab023 intel/compiler: Use a struct for brw_compile_cs parameters
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 05933fb0f7 intel/compiler: Use INTEL_DEBUG=blorp to dump blorp shaders
Make INTEL_DEBUG=blorp dump the blorp shaders instead using the
general INTEL_DEBUG=fs,vs, which is now reserved to the actual FS and
VS shaders used by the pipeline.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 7fb1e58651 intel/compiler: Make visitors take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 758eb18c6f intel/compiler: Make vec4 generator take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 244d2daa00 intel/compiler: Make brw_postprocess_nir take debug_enabled as a parameter
The callers already have this value, and we would like to make it
follow different rules other than stage that might not be visible to
the helper function, so just pass explicitly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 82d77f0ea8 intel/compiler: Refactor the shader INTEL_DEBUG checks
Make the check once in a variable, that can be reused for other parts.
Also add `unlikely` to the various conditionals depending on it

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 57d664245e intel/compiler: Use a struct for brw_compile_vs parameters
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho f5e1765f98 intel/compiler: Use a struct for brw_compile_fs parameters
Makes calling code more explicit about what is being set, and allows
take advantage of zero initialization for the ones the callsite don't
care.

Besides moving to the struct, two extra "ergonomic" changes were done:

- Add a new shader_time boolean, so shader_time_index is ignored when
  unused -- this allow taking advantage of the zero initialization of
  unset fields.

- Since we have a struct, provide space for the error_str pointer.
  Both iris and i965 were using it, and the extra rstrdup in case of
  failure shouldn't be a burden for the others.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Caio Marcelo de Oliveira Filho 84c3d68344 intel/compiler: Make vue_map parameter const for brw_compile_fs
Just a documentation hint that the VUE map is not modified.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9779>
2021-03-24 23:18:46 +00:00
Samuel Pitoiset 50b5a9a4a0 anv: use common entrypoints for VK_KHR_create_renderpass2
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9601>
2021-03-24 11:21:53 +00:00
Mauro Rossi cb4287608a android: anv: add libcutils shared dependency
My previous patch merged as 2b1930a50a was incomplete

Fixes the following building error:

FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/vulkan.anv_intermediates/LINKED/vulkan.anv.so
...
ld.lld: error: undefined symbol: property_get
>>> referenced by os_misc.c:193 (external/mesa/src/util/os_misc.c:193)
>>>               os_misc.o:(os_get_option) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_util_intermediates/libmesa_util.a

Cc: 21.0 <mesa-stable@lists.freedesktop.org>
Fixes: eeecc21d93 ("util: Add property_get() fallback for android")
Fixes: 2b1930a50a ("android: radv: add libcutils shared dependency")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9744>
2021-03-22 22:52:13 +01:00
Marcin Ślusarz b0452f150e intel/aub_viewer: fix decoding of sampler states
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz 186301a232 intel/aub_viewer: drop bogus check
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz 2b5f9602b7 intel/aub_viewer: catch invalid sampler state pointer
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz 08f8677b29 intel/batch_decoder: assert on invalid sampler pointer
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz 56cd91bc7c intel/batch_decoder: fix decoding of sampler states
There's only 1 sampler state behind
3DSTATE_SAMPLER_STATE_POINTERS[_VS|_HS|_DS|_GS|_PS] and
3DSTATE_SAMPLER_STATE_POINTERS.[PointertoVSSamplerState|PointertoPSSamplerState|PointertoGSSamplerState].

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz cd0f9cdb6e intel/batch_decoder: drop bogus check
state_addr == bo.addr, bo.size==0 is handled by another check

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Marcin Ślusarz bb8ee5f52d intel/batch_decoder: catch invalid sampler state pointer
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9707>
2021-03-22 08:36:55 +00:00
Jason Ekstrand 731ea06758 intel/tools: Handle BINDING_TABLE_POOL_ALLOC in batch decoding
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:46:50 -05:00
Jason Ekstrand 79d9c914ae intel/genxml: Make BindingTablePoolEnable a bool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:46:50 -05:00
Jason Ekstrand 05e133a84a intel/tools: Handle GT_MODE in the batch decoder
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:46:50 -05:00
Jason Ekstrand b2421f7b44 intel/tools: Handle milti-LRI in the batch decoder
Context batches tend to have a lot of multi-LRI and, if we want to be
able to parse those registers nicely, we really handle it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:33:18 -05:00
Jason Ekstrand 65077cdf57 intel/genxml: Binding table pointers are 15 bits on GFX version 12.5+
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:33:16 -05:00
Kenneth Graunke 6fb93465bd intel/genxml: Add a partial GT_MODE definition for Gen11+.
I chose to drop "HW" from the name of this field because on Gen11
it applies to both HW and SW binding tables, so it's a bit of a
misnomer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
2021-03-20 12:32:55 -05:00
Jordan Justen 16d453da7f genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
2021-03-19 09:07:37 +00:00
Michel Dänzer 05bf12ccb6 intel/tools: Use subprocess.Popen to read output directly from a pipe
Instead of using tempfiles to communicate between child & parent
process. The latter sometimes resulted in hitting the meson timeout if
there was high filesystem pressure.

Fixes: ccaa5b034f "intel/tools: rewrite run-test.sh in python"
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9528>
2021-03-19 08:50:37 +00:00
Lionel Landwerlin 9d947127d3 anv: use the device size of CS prefetch to pad secondary buffer calls
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
2021-03-18 20:08:45 +00:00
Lionel Landwerlin 33bc2977e5 intel/mi_builder: use device info to use the right CS prefetch size
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
2021-03-18 20:08:45 +00:00
Lionel Landwerlin beb680aae4 intel/dev: store size of CS prefetch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9679>
2021-03-18 20:08:45 +00:00
Jordan Justen df5607d2ef anv: Use fallback paths if DRM_I915_QUERY_ENGINE_INFO fails
Anvil can handle if this call fails, but not if we assert. :)

Reported-by: Brian Paul <brianp@vmware.com>
Fixes: 5d84c764fd ("anv: Gather engine info from i915 if available")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9664>
2021-03-18 00:54:29 +00:00
Jason Ekstrand 91192696e6 intel/fs: Add support for 16-bit A64 float and integer atomics
The messages for those 16-bit operations still use 32-bit sources and
destinations, so expand them accordingly when building the payload.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8750>
2021-03-18 00:13:40 +00:00
Lionel Landwerlin 8b6d22109f intel/fs/vec4: add missing dependency in write-on-write fixed GRFs
If we load constant data using pull constant SENDS, and we later load
that register with some other data, we can end up in a situation where
we don't track the initial fixed register write and therefore end up
using uninitialized registers.

This tracks write-on-write of fixed GRFs like we do for normal virtual
GRFs.

v2: Fix post_alloc_reg case (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9667>
2021-03-17 23:25:02 +00:00
Jason Ekstrand 4079279051 anv/apply_pipeline_layout: Add support for A64 descriptor access
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8635>
2021-03-17 17:49:59 +00:00