Commit Graph

137677 Commits

Author SHA1 Message Date
Corentin Noël 4e5ea37612 ci: Use lavacli from master
This allows to fix some credential leaks and provides compatibility with
the latest LAVA version.

Avoids failures when the LAVA instance returns Error 500

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9851>
2021-04-07 17:26:29 +00:00
Samuel Pitoiset d4db68b338 radv: enable DCC stores with MSAA 4x/8x on GFX10+
Should work now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10052>
2021-04-07 17:13:51 +00:00
Alyssa Rosenzweig 1286e73c2c nir/lower_idiv: Add 8-bit and 16-bit lowering path
Roundtrip to a larger float and divide there. The extra details for
mod/rem are handled directly in integer space to simplify verification
of rounding details. The one issue is that the mantissa might be
rounded down which will cause issues; adding 1 unconditionally (proposed
by Jonathan Marek) fixes this. The lowerings here were tested
exhaustively on all pairs of 16-bit integers.

v2: Update idiv lowering per Rhys Perry's comment.

v3: Rewrite lowerings.

v4: Remove useless ftrunc, fix 8-bit issue, simplify code.

v5: Remove useless ffloor

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig e91dec1327 nir/lower_idiv: Factor out numer/denom load
No need to duplicate across paths.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig 7b0eb4aa00 nir/lower_idiv: Convert to lower_instructions
Helps deduplicate some code between the two lowering paths. In
particular, it ports the missing 32-bit? check to the precise pass. This
does not change anything immediately: drivers depending on this to lower
16-bit did not work before due to type mismatches and will not work now
since it'll refuse to lower. But that means sub-32-bit idiv can be
lowered more efficiently in an algebraic pass.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig e4da24bd24 nir: Add {i2f, u2f, f2i, f2u} helpers
Convenient for bitsize independent lowerings, will be used in the idiv
lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Alyssa Rosenzweig 6b19711645 nir: Add nir_type_convert
Generalizes nir_convert_to_bit_size, which we implement as a
special-case.

v2: Take a sized dest type but allow unsized or sized source to address
Jason's feedback. Shorten name.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8339>
2021-04-07 15:48:15 +00:00
Samuel Pitoiset f280367a27 radv: perform MSAA color decompression for storage images with DCC
For MSAA storage images with DCC, we also need to perform a MSAA
color decompression.

Fixes dEQP-VK.pipeline.multisample.storage_image.* if DCC stores
is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9854>
2021-04-07 15:35:07 +00:00
Rhys Perry 835c5b7ebf aco: fix integer tg4 workaround with unnormalized coordinates
Same as LLVM from 2abf62d348.

fossil-db (GFX8):
Totals from 15 (0.01% of 147787) affected shaders:
VGPRs: 744 -> 748 (+0.54%)
CodeSize: 100472 -> 100732 (+0.26%)
Instrs: 19995 -> 20059 (+0.32%)
Latency: 1001530 -> 1001859 (+0.03%)
InvThroughput: 378508 -> 378747 (+0.06%)
SClause: 676 -> 675 (-0.15%)
Copies: 1655 -> 1654 (-0.06%)
PreSGPRs: 735 -> 742 (+0.95%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10053>
2021-04-07 15:21:51 +00:00
Connor Abbott 5a70c4d4a0 ir3: Don't copy propagate arrays in ir3_cp
We don't check whether there's an intervening write in this pass, which
makes it incorrect. ir3_cp_postsched does check correctly, but we were
accidentally doing it here anyway for some sources.

While we're here, delete some code that was only used in the array case.

Fixes: f370e954 ("freedreno/ir3: handle const/immed/abs/neg in cp")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Connor Abbott 1ad5ee5a04 ir3/cp_postsched: Set address of uses for relative mov's
Fixes: 680ca5b ("freedreno/ir3: add post-scheduler cp pass")
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Connor Abbott dcc26a3945 ir3: Fix valid flags for STIB
Disallow immediates for the source. This was hidden by the fact that we
didn't copy-propagate trivial collect instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Connor Abbott 94beaa1d92 ir3/legalize: Fix last input (ss) insertion
If there was a mix of ldlv and bary.f and we inserted an (ss) *after*
the last input which was a bary.f, then last_input_needs_ss would get
unset, even though it shouldn't. For figuring out whether we need the
(ss), we need to know whether there are any pending ldlv's when
last_input gets executed, not at the end of the block, which means that
the existing code's strategy of inserting it after the whole block has
been processed won't work. Rework it to do the last_input processing in
the main loop instead.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Connor Abbott 35ffe4fec1 freedreno/a3xx: Fix SP_FS_CTRL_REG1_INITIALOUTSTANDING
Unfortunately this didn't fix anything, but I thought I might as well
include it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Connor Abbott 8cd7950014 util/bitset: Avoid out-of-bounds reads
I missed a corner case here: when the next range ends right at the end
of the bitset, we need to return immediately to avoid trying to search
after the bitset. And when finding the next end, we similarly need to
bail if the range is size 1 at the very end of the range. In practice
this probably would'nt have been noticed, because it would break out of
the loop anyway, but I happened to be running something using this under
Valgrind and it complained.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10076>
2021-04-07 14:35:13 +00:00
Mike Blumenkrantz 387189a955 intel: avoid dumping null cs sampler/binding states
this crashes the driver

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10077>
2021-04-07 14:24:08 +00:00
Rhys Perry 7ebb215495 nir_to_tgsi: run constant folding after nir_opt_algebraic
Otherwise, an infinite loop can occur.

The first nir_opt_algebraic in the loop can optimize:
op(bcsel(a, #b, c), #d) to bcsel(a, op(b, d), op(c, d))
which (because op(b, d) is not constant folded), will be reverted by the
second nir_opt_algebraic in the loop.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10071>
2021-04-07 13:55:31 +00:00
Jason Ekstrand 26c3a509de intel: Drop gen_device_info::has_resource_streamer
We've never done anything with that HW and it was removed in ICL.
There's no point in carrying around the useless field.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10069>
2021-04-07 13:33:18 +00:00
Michel Dänzer 8ec530d982 wsi/x11: Wait for fences with IMMEDIATE on Xwayland
The commit below was already meant to do this, but accidentally missed
this part.

Fixes stutter when the frame-rate drops below the refresh rate.

Fixes: e8f50bd600 "wsi/x11: Treat IMMEDIATE present mode the same as
                     MAILBOX for Xwayland"

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10026>
2021-04-07 13:20:20 +00:00
Danylo Piliaiev 519eb735a3 turnip: implement variableMultisampleRate
If subpass doesn't have depth/color attachments - samples count is
devised from VkPipelineMultisampleStateCreateInfo::rasterizationSamples.
Without variableMultisampleRate enabled all pipelines in such subpass
should have the same samples count; variableMultisampleRate allows
to have pipelines with different number of samples in one subpass,
given that it doesn't have depth/color attachments.

Blob doesn't have it enabled but there is no known reason for this.

Passes:
 dEQP-VK.pipeline.multisample.variable_rate.*

Fixes test:
 dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9556>
2021-04-07 12:04:45 +00:00
Tomeu Vizoso f31a84233b ci: Don't retry failed test runs
After a recent LAVA update, failures in running a test would cause the
whole test to be retried. We only want for the boot to be retried (in
case of infrastructuer errors), so set the nr of retries for tests to 1.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9950>
2021-04-07 13:36:14 +02:00
Tomeu Vizoso 4297fe1d9d ci: Set more reasonable timeouts for LAVA jobs
The test timeout shouldn't be bigger than the whole job's timeout.

Also, reduce the timeouts to a more sane level and remove timeouts that
don't bring value.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9950>
2021-04-07 13:36:14 +02:00
Tomeu Vizoso 93ec399b28 ci: Use a single template for LAVA jobs
It's a pain to keep both templates in sync and there aren't really that
many differences.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9950>
2021-04-07 13:34:14 +02:00
Mike Blumenkrantz 8926c4a313 aux/trace: add a set_inlinable_constants hook
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10057>
2021-04-07 10:30:00 +00:00
Juan A. Suarez Romero eddbbd8b68 v3d: use uint type in _gen_unpack_uint
Use a unsigned int type in the loop to avoid unintended sign extensions.

Fixes CID#1414500 (Unintended sign extension [SIGN_EXTENSION]).

Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10060>
2021-04-07 09:39:42 +00:00
Boris Brezillon d760a995e3 panfrost: Hook up indirect draw support
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8700>
2021-04-07 08:27:58 +00:00
Boris Brezillon 54526d8eca panfrost: Prepare things for indirect draws
Several things need to be tweaked to re-use existing helpers for
indirect draws:

* Indirect draws should always be considered as instanced draws since
  we don't know in advance how many instances will be requested. For
  each vertex attribute buffer entry we store the element divisor which
  will be extracted by the compute shader and transformed into a HW
  divisor

* PRIMITIVE.index_count should be initialized to its default value
  (one, or zero after the minus(1) modification) waiting for the
  compute shader to patch it

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8700>
2021-04-07 08:27:58 +00:00
Boris Brezillon 2e6d94c198 panfrost: Add helpers to support indirect draws
Indirect draws are implemented with compute jobs patching the
vertex/tiler jobs. Provide helpers to do that.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8700>
2021-04-07 08:27:58 +00:00
Boris Brezillon 9a08c9097f panfrost: Stop including pan_device.h from pan_bo.h
We want to define structures containing pan_pool objects in pan_device.h
but it is prevented by the

      pan_device.h -> pan_pool.h -> pan_bo.h
          ^____________________________|

loop.

Break this loop by not including pan_device.h from pan_bo.h.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8700>
2021-04-07 08:27:58 +00:00
Pierre-Eric Pelloux-Prayer 363c1ef0c0 gallium/u_threaded: split draws that don't fit in a batch
Multidraws with large draw count will try to call tc_add_slot_based_call
with a payload larger than TC_CALLS_PER_BATCH.

This commit split these draws in multiple commands to avoid this issue.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4534
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9920>
2021-04-07 08:00:36 +00:00
Boris Brezillon e25daef16f panfrost: Skip disabled RTs when selecting a RT for transaction elimination
If the render target is disabled, the CRC won't be updated, and the
slice state should stay unchanged.

Fixes dEQP-GLES2.functional.fbo.render.shared_colorbuffer.tex2d_rgba_stencil_index8
and dEQP-GLES2.functional.fbo.render.shared_colorbuffer.rbo_rgba4_depth_component16.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9907>
2021-04-07 09:44:50 +02:00
Boris Brezillon 13ff5756ae panfrost: Don't reserve space in the color buffer for disabled RTs
Render targets that have no clear or draws are disabled and thus don't
use the color buffer. Don't reserve space for those.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9907>
2021-04-07 09:44:37 +02:00
Marek Olšák c105c8ad2c winsys/amdgpu: remove another 8 bytes from amdgpu_winsys_bo by packing better
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 815d98c22d gallium/pb: remove 8 bytes from pb_buffer by packing variables
Only svga used usages beyond 16 bits. All other drivers are OK with 16 bits.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 712b629abf gallium/pb: change pb_buffer::alignment to alignment_log2
Alignments are always 2^n, so store n = log2(alignment). The next commit
will take advantage of the saved space.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 3d0a4864ce winsys/amdgpu: add amdgpu_cs::ws to reduce dereferences
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák d5b877619d winsys/amdgpu: remove amdgpu_winsys_bo::ws
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 65495e6caa radeon_winsys.h: add a winsys parameter to most winsys buffer functions
This will allow removing the winsys pointer from buffers.

The amdgpu winsys adds dummy_ws to get radeon_winsys because there can be
no radeon_winsys around (e.g. while amdgpu_winsys is being destroyed), but
we still need some way to call buffer functions.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák aed8af5456 radeon_winsys.h: add a new function radeon_bo_reference that takes a winsys
This will allow removing the winsys pointer from buffers.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 522938f271 winsys/radeon: rename radeon_bo_reference -> radeon_ws_bo_reference
radeon_bo_reference will be a new function in radeon_winsys.h.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Marek Olšák 6c6a39682e gallium/pb: pass an optional winsys pointer to the buffer destroy function
This will allow removing the winsys pointer from buffers.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9809>
2021-04-06 22:31:15 +00:00
Lionel Landwerlin 33b2daab1a intel/compiler: lower bit sizes in NIR postprocessing
It appears that between preprocess & postprocess some descriptor
lowering introduces 8bit types in the shader, so run the lower bit
size again to make sure we don't have any unsupported types in our
shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e06144a818 ("anv: Use 64bit_global_32bit_offset for SSBOs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4478
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9705>
2021-04-06 23:21:30 +03:00
Alyssa Rosenzweig d01628d24d pan/bi: Remove conversion lowering
Inherited from Midgard, it's easier to just do at NIR->BIR time now that
we have a builder that doesn't suck. Impeded certain optimizations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Alyssa Rosenzweig 266de379c2 pan/bi: Generalize f2i16, f2u16
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Alyssa Rosenzweig be74b84e6f pan/bi: Fill in some more conversions
The trick is that downcasts are just swizzling out what you don't want,
so things like U32_TO_F16 can be synthesized as V2U16_TO_V2F16 with
src.h00

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Alyssa Rosenzweig 435800e750 pan/bi: Lower swizzles
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Alyssa Rosenzweig e3e2c5b594 pan/bi: Optimize MKVEC.v2i16 generation
Prefer SWZ.v2i16 in cases where that's possible, it will be easier to
optimize later.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Alyssa Rosenzweig f9bc168bd3 pan/bi: Add bi_swz_16 helper
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10065>
2021-04-06 19:35:33 +00:00
Marek Olšák 6bc7a0b366 radeonsi: fix si_compute_copy_image if DCC decompression happens before a copy
The buffer clear after DCC decompression overwrote user SGPRs that we set
here, leading to invalid image coordinates. Set them after we bind images.

This will actually be fixed by "radeonsi: don't decompress DCC for float
formats in si_compute_copy_image" as well.

Fixes: ad71ef9326 "radeonsi: don't use a constant buffer for the copy_image compute shader"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4583

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10061>
2021-04-06 19:19:56 +00:00
Mike Blumenkrantz fc7ce9b636 zink: drop VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT from compute path
this was dropped a while ago from gfx but I failed to pick it up for compute

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10062>
2021-04-06 18:11:08 +00:00