Commit Graph

161336 Commits

Author SHA1 Message Date
Mark Collins 09ae2c4fee tu: Optimize hash_renderpass_instance by removing XXH64_update
It was determined through testing that `XXH64_update` is
significantly slower than calling `XXH64` directly as far as small
data velocity is concerned. This function is called on every RP end
which made it visible while profiling but substantial difference
(measured to be ~4x) made it not show up whatsoever.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18428>
2022-10-18 16:28:29 +00:00
Tapani Pälli b02e9ef35a anv: fill AlphaToCoverageEnable lazily from state
Now the first blend state is filled only when emitted.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19105>
2022-10-18 10:44:57 +03:00
Tapani Pälli 9f75355643 anv: move emit_shading_rate to gfx8_cmd_buffer
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19105>
2022-10-18 10:44:38 +03:00
Yonggang Luo 83ebd637d5 d3d10ump: No need define snprintf anymore in InputAssembly.cpp
As minimal visual studio version are 2019

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18685>
2022-10-18 03:16:00 +00:00
Yonggang Luo a9da108c6b nir: No need redefine snprintf anymore in nir.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18685>
2022-10-18 03:16:00 +00:00
Yonggang Luo 1ee21139e8 gallium: delete graw
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7017

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19099>
2022-10-18 01:57:27 +00:00
Timothy Arceri ac7f4e0942 glsl/glsl_to_nir: remove unreachable code
This hack in glsl_to_nir() to clean up after the glsl ir linker should
no longer be reachable. These type of linking opts are now done via
a nir based linker long after GLSL IR has been coverted to nir by
this pass.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19104>
2022-10-18 00:05:29 +00:00
Sergei Chernyadyev c7e9268658 radv: fix setting results for initialization failures in thread trace and trap handler
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19083>
2022-10-17 22:59:15 +00:00
nyanmisaka 0e782d9609 radeonsi: Inherit the old modifier when reallocating the texture.
Otherwise the reallocated texture has an invalid modifier when exporting
the VAAPI surface handle.

Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19097>
2022-10-17 21:50:37 +00:00
Luis Felipe Strano Moraes 5bc52a9103 anv: fix FTBFS on grl due to changes in clang 15
This was causing build failures when RT is enabled on recent Fedora releases.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7404

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19094>
2022-10-17 21:27:19 +00:00
Alyssa Rosenzweig 2c7be4d421 nir: Usher nir_normalize_cubemap_coords into 2022
I stumbled upon this old NIR pass (still in use by intel and broadcom)
and noticed how most of the code was NIR boilerplate that we have
helpers for. Rewrite the pass to use all the helpers.

v2: Fix cube map arrays.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18754>
2022-10-17 20:46:24 +00:00
Alyssa Rosenzweig fc5c671e87 nir: Fix nir_fmax_abs_vec_comp
This failed to take fabs of the first component, implementing an unintended
formula that would return the right results in some common cases but is wrong in
general:

   max { x, |y|, |z| }

instead of the intended

   max { |x|, |y|, |z| }

Reexpress the implementation to make correctness obvious.

Fixes: 272e927d0e ("nir/spirv: initial handling of OpenCL.std extension opcodes")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18754>
2022-10-17 20:46:24 +00:00
Sil Vilerino 6fbb87851c d3d12: HEVC Set D3D12_VIDEO_ENCODER_CODEC_CONFIGURATION_HEVC_FLAG_USE_ASYMETRIC_MOTION_PARTITION when required by caps
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19119>
2022-10-17 20:33:19 +00:00
Sil Vilerino 8f654b9000 d3d12: Fix HEVC wrong caps detection due to bad parenthesis in condition
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19119>
2022-10-17 20:33:19 +00:00
Sil Vilerino be7e2e5525 d3d12: HEVC Encode workaround for edge case in caps reporting not contemplated by upper layer interface
Workaround for https://github.com/intel/libva/issues/641

Example where VAConfigAttribValEncHEVCBlockSizes.max_transform_hierarchy_depth_intra/inter overflows

MinCbLog2SizeY = log2(8) = 3
CtbLog2SizeY = log2(64) = 6
MinTbLog2SizeY = log2(4) = 2
MaxTbLog2SizeY = log2(32) = 5

max_transform_hierarchy_depth_intra = (CtbLog2SizeY − MinTbLog2SizeY) = 4
max_transform_hierarchy_depth_inter = (CtbLog2SizeY − MinTbLog2SizeY) = 4

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19119>
2022-10-17 20:33:19 +00:00
Danylo Piliaiev 3eed5931ed tu: Fix the size of patch control points state
tu6_emit_patch_control_points was called with CS size calculated
at compile time, but HS params have dynamic size. Account for this.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7479

Fixes: 68f3c38c80
("tu: Implement extendedDynamicState2PatchControlPoints")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19075>
2022-10-17 20:13:43 +00:00
Daniel Schürmann ebf7f7a182 aco/spill: Fix spilling of Phi operands
By adding the renamed variable, phi operands got spilled twice at the precessors.

Fixes: dEQP-VK.ray_query.misc.dynamic_indexing
Closes: #7493
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19109>
2022-10-17 19:50:32 +00:00
Alyssa Rosenzweig 829f769e60 pan/mdg: Fix 16-bit alignment with spiller
The loop over sources has to happen for every instruction, regardless of whether
we also need to register allocate the destination. The other source loops handle
this properly, but this one was missed.

Fixes spilling failure in shaders/android/angle/aztec_ruins/16.shader_test when
the input NIR is shuffled a bit (from reordering passes).

Fixes: 129d390bd8 ("pan/mdg: Fix bound setting in RA for sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19093>
2022-10-17 19:11:10 +00:00
Alyssa Rosenzweig 2c446b6636 pan/mdg: Limit work registers for large workgroups
When more than 8 registers are used, Midgard can only fit 64 threads in a
thread group. For barriers to work properly, a threadgroup must fit an entire
work group. The GL driver configures the hardware to have threadgroups the size
of work groups. That means if more than 64 threads are used in a workgroup, and
more than 8 registers are used, the hardware will fault spawning threads.

To workaround this hardware limitation, we need to limit the number of work
registers used depending on the size of the workgroup. Typically, the work group
size is known at compile-time so that determination can usually be made without
variants. To avoid variants, we make a pessimistic estimate in the case when
it's not known at compile-time.

shader-db shows 6 shaders affected. I expect that all of these would fault with
DATA_INVALID_FAULT if they tried to execute before this patch, due to the
oversize local size, and faulting is even slower than spilling ;-)

Fixes dEQP-GLES31.functional.synchronization.* on Mali-T860.

instructions HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 121 -> 157 (29.75%)
instructions HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 121 -> 157 (29.75%)
instructions HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 141 -> 184 (30.50%)
instructions HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 141 -> 184 (30.50%)
instructions HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 513 -> 933 (81.87%)
instructions HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 505 -> 1002 (98.42%)

bundles HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 73 -> 116 (58.90%)
bundles HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 73 -> 116 (58.90%)
bundles HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 61 -> 97 (59.02%)
bundles HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 61 -> 97 (59.02%)
bundles HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 281 -> 701 (149.47%)
bundles HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 278 -> 775 (178.78%)

registers helped:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 11 -> 8 (-27.27%)
registers helped:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 11 -> 8 (-27.27%)
registers helped:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 14 -> 8 (-42.86%)
registers helped:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 14 -> 8 (-42.86%)
registers helped:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 16 -> 8 (-50.00%)
registers helped:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 16 -> 8 (-50.00%)

threads helped:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)
threads helped:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 1 -> 2 (100.00%)

spills HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 0 -> 5
spills HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 0 -> 5
spills HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 0 -> 8
spills HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 0 -> 8
spills HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 0 -> 112
spills HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 0 -> 146

fills HURT:   shaders/android/gfxbench/carchase/6.shader_test MESA_SHADER_COMPUTE: 0 -> 26
fills HURT:   shaders/android/gfxbench/carchase/386.shader_test MESA_SHADER_COMPUTE: 0 -> 26
fills HURT:   shaders/android/gfxbench/carchase/374.shader_test MESA_SHADER_COMPUTE: 0 -> 33
fills HURT:   shaders/android/gfxbench/carchase/4-1.shader_test MESA_SHADER_COMPUTE: 0 -> 33
fills HURT:   shaders/android/com.miHoYo.GenshinImpact/18.shader_test MESA_SHADER_COMPUTE: 0 -> 209
fills HURT:   shaders/android/com.miHoYo.GenshinImpact/16.shader_test MESA_SHADER_COMPUTE: 0 -> 234

total instructions in shared programs: 1521691 -> 1522766 (0.07%)
instructions in affected programs: 1542 -> 2617 (69.71%)
helped: 0
HURT: 6
HURT stats (abs)   min: 36.0 max: 497.0 x̄: 179.17 x̃: 43
HURT stats (rel)   min: 29.75% max: 98.42% x̄: 50.13% x̃: 30.50%
95% mean confidence interval for instructions value: -49.36 407.69
95% mean confidence interval for instructions %-change: 17.14% 83.12%
Inconclusive result (value mean confidence interval includes 0).

total bundles in shared programs: 649296 -> 650371 (0.17%)
bundles in affected programs: 827 -> 1902 (129.99%)
helped: 0
HURT: 6
HURT stats (abs)   min: 36.0 max: 497.0 x̄: 179.17 x̃: 43
HURT stats (rel)   min: 58.90% max: 178.78% x̄: 94.01% x̃: 59.02%
95% mean confidence interval for bundles value: -49.36 407.69
95% mean confidence interval for bundles %-change: 36.20% 151.83%
Inconclusive result (value mean confidence interval includes 0).

total registers in shared programs: 90681 -> 90647 (-0.04%)
registers in affected programs: 82 -> 48 (-41.46%)
helped: 6
HURT: 0
helped stats (abs) min: 3.0 max: 8.0 x̄: 5.67 x̃: 6
helped stats (rel) min: 27.27% max: 50.00% x̄: 40.04% x̃: 42.86%
95% mean confidence interval for registers value: -8.03 -3.30
95% mean confidence interval for registers %-change: -50.95% -29.13%
Registers are helped.

total threads in shared programs: 55717 -> 55723 (0.01%)
threads in affected programs: 6 -> 12 (100.00%)
helped: 6
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
95% mean confidence interval for threads value: 1.00 1.00
95% mean confidence interval for threads %-change: 100.00% 100.00%
Threads are helped.

total spills in shared programs: 1108 -> 1392 (25.63%)
spills in affected programs: 0 -> 284
helped: 0
HURT: 6

total fills in shared programs: 4721 -> 5282 (11.88%)
fills in affected programs: 0 -> 561
helped: 0
HURT: 6

Cc: mesa-stable
Closes: #7228
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>
2022-10-17 18:56:13 +00:00
Alyssa Rosenzweig 9b19104a30 pan/mdg: Lower PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK on Midgard
The register file on Midgard is not large enough to sustain 256 threads in a
threadgroup when all ISA-defined registers are used. As such, we want
to advertise the smallest MAX_THREADS_PER_BLOCK permissible by the spec to
avoid compiling shaders that will necessarily spill. The minimum-maximum in
OpenGL ES 3.1 is 128, so set that on Midgard.

6 compute shaders LOST in shader-db due to exceeding this new limit. These
shaders would fault if they were attempted to be executed.

Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>
2022-10-17 18:56:13 +00:00
Alyssa Rosenzweig 5c95be85ab panfrost/ci: Remove stale fail
Due to fractional run. This whole section passes.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19092>
2022-10-17 18:56:13 +00:00
Rohan Garg 16d061d3ac anv: Enable 16 bit float ops on devices that have a LSC
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17988>
2022-10-17 15:56:29 +02:00
Rohan Garg 43169dbbe5 intel/compiler: Support 16 bit float ops
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17988>
2022-10-17 15:56:28 +02:00
Daniel Stone 2e774180c6 Revert "panfrost/ci: Disable t720 jobs"
This reverts commit b3a69d1c31.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19113>
2022-10-17 12:13:47 +01:00
Alejandro Piñeiro c1cb7506bb v3dv/pipeline: keep qpu_insts around if we expect them to be used later
If the pipeline was created with the creation flags
VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR or
VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR it is
really likely that methods from VK_KHR_pipeline_executable_properties
that would require having access to the qpu insts around will be
called.

Instead of getting those back from the BO where we upload them, we
just keep them around. This could require more host memory, but would
allow us to avoid needing to handle map/unmap the BO when needed (so
needing the host memory in any case). This can be tricky if those
methods are being called from different threads (so we can avoid
adding a mutex there).

In the same way, if the pipeline was not created with those flags, we
skip collecting data that requires the QPU. Only
GetPipelineExecutableProperties is allowed to be called without any of
those flags, and doesn't require that info.

This fixes a race condition crash at GetPipelineExecutableProperties
when using fossilize-replay with some fossils with several shaders,
and using several threads, as some thread would be unmapping the bo
before other thread stopped to use it.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18859>
2022-10-17 10:06:23 +00:00
Timothy Arceri 7dcdd51938 glthread: leave dlist dispatch in place for Begin/End
If Begin/End are called from a display list make sure to leave
the dlist.c's dispatch table in place just like the non-glthread
code does.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7335
Fixes: 7f1cac7ba6 ("mesa/glthread: enable immediate mode")

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19088>
2022-10-17 09:31:12 +00:00
Samuel Pitoiset ca02da294a radv: discard the PS epilog when the pipeline doesn't use a fragment shader
This makes no sense and this was broken.

Fixes dEQP-VK.mesh_shader.ext.smoke.*_lib.mesh_shader_triangle_rasterization_disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19019>
2022-10-17 08:13:26 +02:00
Samuel Pitoiset 7b3aae8912 radv: do not create a noop FS when the FS is imported from a library
The entrypoint can be NULL even if the FS is imported from a library,
but we shouldn't overwrite the pre-compiled FS by a noop.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19019>
2022-10-17 08:13:24 +02:00
Jose Maria Casanova Crespo c8849043a8 Revert "CI: Igalia farm is down"
This reverts commit aa405b789e.

Igalia farm is up again. Switch died and it needed to be replaced.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19102>
2022-10-17 02:02:01 +02:00
Timothy Arceri 675bcbb7a1 mesa: add EXT_debug_label support
KHR_debug provides the same functionality but this extension is
still in use and adding support for it seems fairly harmless.

For example its used by Unity and without it we keep
getting given apitraces from Unity games that just spew out
unsupported function errors due to the missing support.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19029>
2022-10-17 08:53:20 +11:00
Yonggang Luo 70fef47633 ci/windows: Getting the default supported windows version to be 7 when using mingw
MSVC are already tested with default windows version 8

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>
2022-10-17 00:36:40 +08:00
Yonggang Luo 79891bea1c ci/windows: Remove -Dlibelf:warning_level=1 as libelf subproject are already removed
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>
2022-10-17 00:28:32 +08:00
Yonggang Luo 2cb21fdd53 ci/windows: Enable gles1 for msvc
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19096>
2022-10-17 00:28:29 +08:00
Konstantin Seurer 6905c25829 radv/rra: Use the accel struct type for header validation
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>
2022-10-16 14:37:02 +00:00
Konstantin Seurer 43756a9f76 radv/rra: Continue dumping accel structs if validation fails
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>
2022-10-16 14:37:02 +00:00
Konstantin Seurer e8547392b0 radv/rra: Add basic header validation
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>
2022-10-16 14:37:02 +00:00
Konstantin Seurer 2ccd039174 radv/rra: Validate before gathering bvh info
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>
2022-10-16 14:37:02 +00:00
Konstantin Seurer d83176d1c0 radv/rra: Fix dumps in the case of aliasing
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19089>
2022-10-16 14:37:02 +00:00
Jose Maria Casanova Crespo aa405b789e CI: Igalia farm is down
It seems a power outage affected the Raspberry Pi farm nodes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19095>
2022-10-16 12:06:25 +02:00
Yonggang Luo 2b64ff9284 util: Turn -DWINDOWS_NO_FUTEX to be pre_args
Turn -DWINDOWS_NO_FUTEX to be pre_args for not need add direct dependencies
to dep_futex for libraries and executables.
So only add dependencies to idep_mesautil is enough.

And this will make sure all source code are either using Windows futex,
or use mtx_t consistently across different sources, other than mixed usage of
futex and mtx_t before this commit.

If -DWINDOWS_NO_FUTEX is not globally available, that would cause
/src/util/simple_mtx.h:116: undefined reference to `futex_wait'

This error is raised when
 * compiled with -D min-windows-version=7
 * moved futex_wait from futex.h to futex.c
 * used simple_mtx_t in more codes

Or linkage error:
src/compiler/libcompiler.a.p/glsl_types.cpp.obj: in function `futex_wake':
/../../src/util/futex.h:154: undefined reference to `WaitOnAddress'
When:
 * compiled with -D min-windows-version=7
 * used simple_mtx_t in more codes

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7494
Fixes: c002bbeb2f ("util: Add a Win32 futex impl")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19087>
2022-10-16 05:21:45 +00:00
Alyssa Rosenzweig 4c7a44413a mesa,gallium: Revert "Make point coord origin a CAP"
This reverts commit e749f67f89, which added a CAP
to support drivers that can only do upside-down point coordinates. That was
added specifically for Asahi, since Metal's point coordinate convention is
opposite Mesa's. Since then, additional reverse-engineering aided by the PowerVR
headers led me to the bit doing the flip in hardware, so Asahi does not use the
CAP since baadc1ec13 ("asahi: Don't use lower_wpos_pntc"). Garbage collect it.

[If it's needed for future hardware, we can revive it. But the plan is Vulkan
anyway.]

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19078>
2022-10-16 02:23:12 +00:00
José Roberto de Souza 86c9aa6bfe intel: Add and use intel_engines_class_to_string()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>
2022-10-15 20:04:51 +00:00
José Roberto de Souza 772dfd60ad intel: Convert i915 engine type to intel in tools/ common/ and ds/
This ones were left to be done after initial conversion.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>
2022-10-15 20:04:51 +00:00
José Roberto de Souza 5269d91efc intel: Convert missing i915 engine types to intel
This convertions were missed due to bad rebased in my end, sorry.

Fixes: 03b959286e ("intel: Make engine related functions and types not i915 dependent")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18975>
2022-10-15 20:04:51 +00:00
Alyssa Rosenzweig ac2964dfbd nir: Be smarter fusing ffma
If there is a single use of fmul, and that single use is fadd, it makes
sense to fuse ffma, as we already do. However, if there are multiple
uses, fusing may impede code gen. Consider the source fragment:

   a = fmul(x, y)
   b = fadd(a, z)
   c = fmin(a, t)
   d = fmax(b, c)

The fmul has two uses. The current ffma fusing is greedy and will
produce the following "optimized" code.

   a = fmul(x, y)
   b = ffma(x, y, z)
   c = fmin(a, t)
   d = fmax(b, c)

Actually, this code is worse! Instead of 1 fmul + 1 fadd, we now have 1
fmul + 1 ffma. In effect, two multiplies (and a fused add) instead of
one multiply and an add. Depending on the ISA, that could impede
scheduling or increase code size. It can also increase register
pressure, extending the live range.

It's tempting to gate on is_used_once, but that would hurt in cases
where we really do fuse everything, e.g.:

   a = fmul(x, y)
   b = fadd(a, z)
   c = fadd(a, t)

For ISAs that fuse ffma, we expect that 2 ffma is faster than 1 fmul + 2
fadd. So what we really want is to fuse ffma iff the fmul will get
deleted. That occurs iff all uses of the fmul are fadd and will
themselves get fused to ffma, leaving fmul to get dead code eliminated.
That's easy to implement with a new NIR search helper, checking that all
uses are fadd.

shader-db results on Mali-G57 [open shader-db + subset of closed]:

total instructions in shared programs: 179491 -> 178991 (-0.28%)
instructions in affected programs: 36862 -> 36362 (-1.36%)
helped: 190
HURT: 27

total cycles in shared programs: 10573.20 -> 10571.75 (-0.01%)
cycles in affected programs: 72.02 -> 70.56 (-2.02%)
helped: 28
HURT: 1

total fma in shared programs: 1590.47 -> 1582.61 (-0.49%)
fma in affected programs: 319.95 -> 312.09 (-2.46%)
helped: 194
HURT: 1

total cvt in shared programs: 812.98 -> 813.03 (<.01%)
cvt in affected programs: 118.53 -> 118.58 (0.04%)
helped: 65
HURT: 81

total quadwords in shared programs: 98968 -> 98840 (-0.13%)
quadwords in affected programs: 2960 -> 2832 (-4.32%)
helped: 20
HURT: 4

total threads in shared programs: 4693 -> 4697 (0.09%)
threads in affected programs: 4 -> 8 (100.00%)
helped: 4
HURT: 0

v2: Update trace checksums for virgl due to numerical differences.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18814>
2022-10-15 17:47:31 +00:00
Mike Blumenkrantz 07c654e08f glthread: fix buffer allocation size with non-signed buffer offset path
this needs to always add the start_offset to avoid creating
buffers that are too small

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18994>
2022-10-15 16:02:38 +00:00
Andri Yngvason 9fc4cb8067 gallium/vl: Add opaque rgb pixel formats
Signed-off-by: Andri Yngvason <andri@yngvason.is>
Reviewed-by: Simon Ser <contact@emersion.fr>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18959>
2022-10-15 08:15:02 +00:00
Erik Faye-Lund 8255739a0a mesa/main: remove driver-cap for ARB_point_sprite
It's always supported, no need for checks here.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Begrudgingly-reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19049>
2022-10-15 02:57:18 +00:00
Erik Faye-Lund 310959d9fe mesa/st: rip out point-sprite cap
All current drivers reports supporting this cap, let's just assume
it's always supported.

It seems better to lower this in the drivers, like we already do for
etnaviv, panfrost and zink...

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Begrudgingly-reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19049>
2022-10-15 02:57:18 +00:00
Italo Nicola b0d698c532 rusticl: correctly check global argument size
As the spec that is quoted in the comment says, if the argument is a
memory object, arg_size should be different than sizeof(cl_mem). The
previous verification only worked if the underlying type has the same
size as sizeof(cl_mem).

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18985>
2022-10-15 02:23:04 +00:00