Commit Graph

83753 Commits

Author SHA1 Message Date
Marek Olšák 63b99590db winsys/amdgpu: implement cs_get_next_fence
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 14:29:30 +02:00
Marek Olšák 04a6cb63aa gallium/radeon: add cs_get_next_fence winsys callback
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 14:29:30 +02:00
Marek Olšák b403eb3385 gallium/radeon: count contexts
We don't wanna use unflushed fences when we have multiple contexts.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 14:29:30 +02:00
Marek Olšák 16d568d911 gallium/radeon: count gfx IB flushes
This will be used as a counter for whether fence_finish needs to flush
the IB.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 14:29:30 +02:00
Marek Olšák c5ff0d3e65 gallium/radeon: move radeon_winsys::cs_memory_below_limit to drivers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák 076db67217 gallium/radeon: inline radeon_winsys::query_memory_usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák 9646ae7799 gallium/radeon/winsyses: expose per-IB used_vram and used_gart to drivers
The following patches will use this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák 1c8f17599e gallium/radeon/winsyses: print CS submission error number
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák 0edc2e433e radeonsi: flush if constant, shader, and streamout buffers use too much memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák c3efdeb8dd radeonsi: flush if sampler views and images use too much memory
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák d82cfab84c radeonsi: deal with high vertex buffer memory usage correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák e62caf576e radeonsi: take compute shader and dispatch indirect memory usage into account
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák c56ecb68e7 radeonsi: take scratch buffer and draw indirect memory usage into account
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák ed2254d157 radeonsi: check IB memory usage of CP DMA operations
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák f4b977bf3d gallium/radeon: add r600_resource::vram_usage and gart_usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Mathias Fröhlich 62d41162bb mesa: Copy bitmask of VBOs in the VAO on gl{Push,Pop}Attrib.
On gl{Push,Pop}Attrib(GL_CLIENT_VERTEX_ARRAY_BIT) take
care that gl_vertex_array_object::VertexAttribBufferMask
matches the bound buffer object in the
gl_vertex_array_object::VertexBinding array.

Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
2016-08-06 06:27:37 +02:00
Nanley Chery c495c18b24 anv/gen7_pipeline: Set PixelShaderKillPixel for discards
According to the IVB PRM Vol2 P1, this bit must be set if a pixel shader
contains a discard instruction.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97207
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-08-05 09:53:52 -07:00
Jason Ekstrand 21f357b66e util/r11g11b10f: Whitespace cleanups
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:07:06 -07:00
Jason Ekstrand ffcf8e1049 util/format: Use explicitly sized types
Both the rgb9e5 and r11g11b10 formats are defined based on how they are
packed into a 32-bit integer.  It makes sense that the functions that
manipulate them take an explicitly sized type.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:07:04 -07:00
Jason Ekstrand c7eb9a7565 util/rgb9e5: Get rid of the float754 union
There are a number of reasons for this refactor.  First, format_rgb9e5.h is
not something that a user would expect to define such a generic union.
Second, defining it requires checking for endianness which is ugly.  Third,
90% of what we were doing with the union was float <-> uint32_t bitcasts
and the remaining 10% can be done with a sinmple left-shift by 23.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:07:01 -07:00
Jason Ekstrand cda8d95660 util/format_rgb9e5: Get rid of the rgb9e5 union
The rgb9e5 format is a packed format defined in terms of slicing up a
single 32-bit value.  The bitfields are far more confusing than simple
shifts and require that we check the endianness.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:06:59 -07:00
Jason Ekstrand f29fd7897a util: Move format_r11g11b10f.h to src/util
It's used from both mesa main and gallium.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:06:57 -07:00
Jason Ekstrand 6c665cdfc5 util: Move format_rgb9e5.h to src/util
It's used from both mesa main and gallium.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-08-05 09:06:31 -07:00
Andres Gomez 591869e921 glsl: fix indentation, comments and line lengths in ast_function.cpp
Acked-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
2016-08-05 14:27:11 +03:00
Andres Gomez 8f98a120f3 glsl: apply_implicit_conversion is static again
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
2016-08-05 14:27:11 +03:00
Andres Gomez 1443c10d74 glsl: struct constructors/initializers only allow implicit conversions
When an argument for a structure constructor or initializer doesn't
match the expected type, only Section 4.1.10 “Implicit Conversions”
are allowed to try to match that expected type.

From page 32 (page 38 of the PDF) of the GLSL 1.20 spec:

  " The arguments to the constructor will be used to set the structure's
    fields, in order, using one argument per field. Each argument must
    be the same type as the field it sets, or be a type that can be
    converted to the field's type according to Section 4.1.10 “Implicit
    Conversions.”"

From page 35 (page 41 of the PDF) of the GLSL 4.20 spec:

  " In all cases, the innermost initializer (i.e., not a list of
    initializers enclosed in curly braces) applied to an object must
    have the same type as the object being initialized or be a type that
    can be converted to the object's type according to section 4.1.10
    "Implicit Conversions". In the latter case, an implicit conversion
    will be done on the initializer before the assignment is done."

v2: Remove also the now redundant constant conversion, the
    constant_record_constructor helper and the replacement code
    (Timothy).

Fixes GL44-CTS.shading_language_420pack.initializer_list_negative

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
2016-08-05 14:27:03 +03:00
Andres Gomez de60d549b9 glsl: Refactor implicit conversion into its own helper
v2: Refactor also the conversion to constant and replacement code
    (Timothy).

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
2016-08-05 14:27:03 +03:00
Andres Gomez af796d756e glsl/types: disallow implicit conversions before GLSL 1.20
Implicit conversions were added in the GLSL 1.20 spec version.

v2: Join the checks for GLSL 1.10 and ESSL (Timothy).

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
2016-08-05 14:27:03 +03:00
Kenneth Graunke 875341c69b i965: Rework the unlit centroid workaround.
Previously, for every input, we moved the dispatch mask to the flag
register, then emitted two predicated PLN instructions, one with
centroid barycentric coordinates (for normal pixels), and one with
pixel barycentric coordinates (for unlit helper pixels).

Instead, we can simply emit a set of predicated MOVs at the top of
the program which copy the pixel barycentric coordinates over the
centroid ones for unlit helper pixel channels.  Then, we can just
use normal PLNs.

On Sandybridge:

total instructions in shared programs: 7538470 -> 7534500 (-0.05%)
instructions in affected programs: 101268 -> 97298 (-3.92%)
helped: 705
HURT: 9 (all of which are SIMD16 programs)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-08-05 01:43:52 -07:00
Tim Rowley b521083ffb swr: [rasterizer core] static analysis fixes for conservative rast
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:35 -05:00
Tim Rowley 68dc544879 swr: [rasterizer core] implement InnerConservative input coverage
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:35 -05:00
Tim Rowley 4034f48833 swr: [rasterizer core] remove CanEarlyZ function
Test is now in SetupPipeline.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley b365989875 swr: [rasterizer core] use 32x32 macrotile for openswr
Significant performance increase (up to 2x) on high geometry workloads.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley 5f4bc9e85b swr: [rasterizer fetch] add support for 24bit format fetch
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley 527d45c8fe swr: [rasterizer fetch] additional fetch format support
Add support for 0 pitch in fetch.

Add support for USCALE/SSCALE for 32bit integer fetches.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley f438b7ba81 swr: [rasterizer jitter] fix potential jit exit crash
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley 57b07498d2 swr: [rasterizer core] update sync handling
Sync now uses a callback to ensure that it's called by the last
thread moving past a DC.  This will help with the new counter
handling.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:38:34 -05:00
Tim Rowley 191786d0f4 swr: [rasterizer core] rename variable
Avoid nested declarations of the same name within a single function.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:01:37 -05:00
Tim Rowley 61cc012e9a swr: [rasterizer jitter] adjust extern "C" block scope
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:01:31 -05:00
Tim Rowley 9f7d99fcfe swr: [rasterizer core] conservative rast degenerate handling
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 14:01:25 -05:00
Tim Rowley f01827a469 swr: [rasterizer core] allow hexadecimal for integer knobs
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-08-04 13:52:12 -05:00
Eric Anholt 49741e1cd2 mesa: Dynamically allocate the matrix stack.
By allocating and initializing the matrices at context creation, the OS
couldn't even overcommit the pages.  This saves about 63k (out of 946k) of
maximum memory size according to massif on simulated vc4
glsl-algebraic-add-add-1.  It also means we could potentially relax the
maximum stack sizes, but that should be a separate commit.

v2: Drop redundant Top update, explain why the stack is small at init
    time.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-08-04 08:52:11 -07:00
Eric Anholt 2a808219b3 state_tracker: Initialize the draw context only when needed.
It's only used for rarely-used deprecated GL features
(feedback/rasterpos), so we can skip the memory allocation and
initialization for it most of the time.

Saves about 659k (out of 1605k) of maximum memory size according to massif
on simulated vc4 glsl-algebraic-add-add-1

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-08-04 08:48:27 -07:00
Eric Anholt c976e164d2 vc4: Move scalarizing and some lowering to link time.
This works out to be a wash in terms of memory usage: We use more memory
to store the separate ALU instructions, but we optimize out a lot of code
as well.  The main result, though, is that we do more of our work at link
time rather than draw time.
2016-08-04 08:48:27 -07:00
Eric Anholt 2350569a78 vc4: Avoid VS shader recompiles by keeping a set of FS inputs seen so far.
We don't want to bake the whole array into the FS key, because of the
hashing overhead.  But we can keep a set of the arrays seen, and use a
pointer to the copy in as the array's proxy.

Between this and the previous patch, gl-1.0-blend-func now passes on
hardware, where previously it was filling the 256MB CMA area with shaders
and OOMing.

Drops 712 shaders from shader-db.
2016-08-04 08:48:27 -07:00
Eric Anholt 62ea2461ed vc4: Don't recompile the CS when the FS changes.
The compiled_fs_id is a proxy for the vc4->prog.fs->input_slots[], but
only the VS dereferences it.

Drops 754 shaders from shader-db.
2016-08-04 08:48:27 -07:00
Eric Anholt d577dbc201 vc4: Move FS inputs setup out to a helper function.
It's a pretty big block, and I was about to make it bigger.
2016-08-04 08:48:27 -07:00
Kenneth Graunke 144cbf8987 nir: Make nir_opt_remove_phis see through moves.
I found a shader in Tales of Maj'Eyal that contains:

        if ssa_21 {
                block block_1:
                /* preds: block_0 */
                ...instructions that prevent the select peephole...
                vec1 32 ssa_23 = imov ssa_4
                vec1 32 ssa_24 = imov ssa_4.y
                vec1 32 ssa_25 = imov ssa_4.z
                /* succs: block_3 */
        } else {
                block block_2:
                /* preds: block_0 */
                vec1 32 ssa_26 = imov ssa_4
                vec1 32 ssa_27 = imov ssa_4.y
                vec1 32 ssa_28 = imov ssa_4.z
                /* succs: block_3 */
        }
        block block_3:
        /* preds: block_1 block_2 */
        vec1 32 ssa_29 = phi block_1: ssa_23, block_2: ssa_26
        vec1 32 ssa_30 = phi block_1: ssa_24, block_2: ssa_27
        vec1 32 ssa_31 = phi block_1: ssa_25, block_2: ssa_28

Here, copy propagation will bail because phis cannot perform swizzles,
and CSE won't do anything because there is no dominance relationship
between the imovs.  By making nir_opt_remove_phis handle identical moves,
we can eliminate the phis and rewrite everything to use ssa_4 directly,
so all the moves become dead and get eliminated.

I don't think we need to check "exact" - just the alu sources.
Presumably phi sources should match in their exactness.

On Broadwell:

total instructions in shared programs: 11639872 -> 11638535 (-0.01%)
instructions in affected programs: 134222 -> 132885 (-1.00%)
helped: 338
HURT: 0

v2: Fix return value to be NULL, not false (caught by Iago).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-08-04 00:42:12 -07:00
Kenneth Graunke 7603b4d3a1 nir: Make nir_alu_srcs_equal non-static.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-08-04 00:41:07 -07:00
Kenneth Graunke 6aa730000f nir: Turn imov/fmov of undef into undef.
On Broadwell:

total instructions in shared programs: 11640214 -> 11639872 (-0.00%)
instructions in affected programs: 17744 -> 17402 (-1.93%)
helped: 78
HURT: 0

total spills in shared programs: 2924 -> 2922 (-0.07%)
spills in affected programs: 104 -> 102 (-1.92%)
helped: 1
HURT: 0

total fills in shared programs: 4394 -> 4389 (-0.11%)
fills in affected programs: 237 -> 232 (-2.11%)
helped: 1
HURT: 0

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-08-04 00:40:59 -07:00