This models instructions closer to the hardware. We'll deduplicate by
the end of the series, but for now this will allow us to add routines
operating on bi_instr without regressing existing users of
bi_instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
RA, DCE, and liveness assume that SSA and non-SSA normal indices are
indexed from 1 in a shared address space, with a maximum given by
bi_max_temp. As a stop gap, let's translate bi_index to old style
node numbers so those passes can be updated cleanly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
We can no longer use the builtin equals, since they're structs now, but
these helpers are almost as convenient.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
These add succinct helpers to generate well-formed references.
Note for semantic that bi_zero represents the immediate value #0, while
bi_null represents a value that does not exist ("undefined").
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
Rather than open-coding indices with manual bit packing flying around,
let's add a data structure corresponding to a reference to some data.
(Think nir_src, ibc_ref, etc). In particular this allows us to pack in
more metadata, like an offset, for properly supporting limited vectors
(for I/O) without bloating the IR with swizzle fields.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
It can be implemented as a constant that just shifts beyond the 64-bits
available for the instruction, and then we can avoid special handling in
a bunch of places.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
Not something we plan to ever support on Bifrost. v7 needs 64-bit
lowered at the NIR level. The support for 64-bit clauses on v6 is iffy
and not worth worrying about at this point.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8215>
Message-passing instructions that read/write staging registers access
either:
* a fixed number of registers
* vecsize registers (/2 for LD/ST_CVT if register_format is 16-bit)
* a computed number for TEXC
This adds the fixed counts into the XML for the first type and space to
specify the latter types.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
Message-passing instructions have an associated message type, which the
clause header needs to signal. Instead of open coding this, let's
annotate the XML. Instructions not otherwise marked do not generate
messages.
Three exceptions apply:
* UBO loads need to use the attribute message type.
* Tile buffer access to Z/S needs ZS message type
* LD_VAR_SPECIAL.fragz needs ZS message type
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
We already use plain neg/abs for this, don't mix it. Will avoid weird
enums for abs/neg with a generated IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
Easy reduction in generated code, while we're at it. Pretty obvious
change after working on similar fixes for the other generators.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
Certain transcendental instructions are not even possible to generate
since these bits are lowered away before the Bifrost backend is touched,
as far as I know.
Job management instructions (most interestingly DOORBELL) do not
correspond to OpenGL/OpenCL/Vulkan.
Segment arithmetic seems mostly useless for real code, any actual use
case I can think of is already covered by indirect loads/stores which
does the segment arithmetic implicitly. I've never seen this in blob
code, probably just a future proofing thing.
Dropping these instructions corresponds to a 3% reduction in generated
lines of code for the printer, builder, and packer for the new IR. Not a
terrible yield for functionality we'll likely never need.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>
Useful for instructions that need to be modeled in the IR (with support
in the builder and printer) but will always be lowered away before
packing since they don't correspond to anything real.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8213>