In some (probably malformed) cases, even weights BOs for strided or depthwise
convolutions can become bigger when using ZRL compression.
To avoid running out of space in the BO, play safe and calculate the
actual optimum ZRL bit count. This does slow compilation for quite a
bit, though (2x slower for MobileNetV1).
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
By using the on-chip SRAM to cache the input image we can save some more
bandwidth and increase the utilization of the NN cores, with the
following improvements:
MobileNetV1: 9.991ms -> 6.2ms
SSDLite MobileDet: 27ms -> 24.3ms
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
We were wrongly counting the remaining number of output channels in the
last superblock, when the former isn't divisible by the latter.
MobileNetV1: 9.991ms -> 9.991ms
SSDLite MobileDet: 32.692ms -> 27ms
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28879>
This function has 2 additional parameters to set spacing before
printing register group dword or individual registers.
intel_print_group() is keept with the same spacing as before so no
changes on decoder output is expected here.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28722>
Xe parser will also need to use the option_color parameter.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28722>
Initial work by Rafael Antognolli <rafael.antognolli@intel.com>
Reworks
- Rebase to main
- Emit the right hiz op for higher mip levels when transitioning the
depth buffer
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28629>
The post-multiplier was extended by 8 bits for improved precision.
The shift offset appears to have changed as well.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28878>
in the case where multiple variables get merged into one, try to use
all the names when creating new vars
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28814>
this creates a reference between variables and their access instrs
before the variables are deleted, which improves debugging
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28814>
With the new hwdb, ETNA_GPU_FEATURES_0 were already queried inside
etna_gpu_new(). Use the stored PIPE_3D feature bit to determine
compatible cores.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28877>
With this, we can drop the duplicated ETNA_GPU_FEATURES_0 query in
screen_create().
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28877>
Test Zink on Venus on Lavapipe.
Acked-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27790>
Moves the lowering of VGRFs into FIXED_GRFs from the code generation
to (almost) right after the register allocation.
This will allow: (1) later passes not worry about VGRFs (and what they
mean in a post reg alloc phase) and (2) make easier to add certain
types of validation post reg alloc phase using the backend IR.
Note that a couple of passes still take advantage of seeing "allocated
VGRFs", so perform lowering after they run.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28604>
This commit adds an implementation of removesuffix so we don't
need the 'str' one which was added in 3.9.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28831>
Bspec 57023: RENDER_SURFACE_STATE::Shader Channel Select Red
"For channels not present in the surface format, the corresponding
Surface Channel Select is either SCS_ZERO or SCS_ONE."
This restriction applies to alpha channel as well if an associated
resource is not used as a render target.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28791>
Bspec 57023: RENDER_SURFACE_STATE:: Shader Channel Select Red
"Render Target messages do not support swapping of colors with
alpha. The Red, Green, or Blue Shader Channel Selects do not
support SCS_ALPHA. The Shader Channel Select Alpha does not support
SCS_RED, SCS_GREEN, or SCS_BLUE."
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28791>
UVD and VCE are separated engines, and not co-exist with VCNs
Fixes: c34cfc1a3b (ac/gpu_info: update multimedia info)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28863>
Use predication instead of branching whenever possible and profitable:
all divergent leaf branches are replaced with predication. Non-divergent
branches are kept since for those a branch might be more performant when
it jumps over all instructions. Although it might be possible to support
a limited form of nested predication, this is more difficult to
implement so we only support leaf branches for now.
When translating from NIR to ir3, predication is emitted just like
normal branches except that the branch is replaced with pred[tf] and the
opposite (pred[ft]) is inserted at the end of the then-block. This
pattern is then recognized during legalization at which point the
closing prede is inserted. We don't insert this right away to allow
opt_jump to optimize jumps out of the else-block. Since the branches we
support for predication always have exactly one block in each arm, the
then-block is emitted first, and blocks are never reordered, this way of
emitting predicated branches ensures they have the correct memory
layout.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27982>
To support predt/predf which always read from p0.x, we need to support
precolored sources for the predicates RA.
This patch implements this as follows: whenever a precolored source is
encountered whose def isn't live in the correct register, reload it into
the correct one. To make sure we don't reload too often, two precautions
are made. First, we precolor all defs of precolored sources and try do
use that register when allocating one for a def. Second, since currently
only p0.x is used for precoloring, we try not to allocate it whenever
there are outstanding precolored defs.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27982>
We used to model predt/predf as taking a predicate register source. The
blob disassembler shows them taking a label argument. However, it seems
that both are incorrect: the condition is always taken from p0.x and I
have not been able to construct a test case were the label makes any
difference.
This patch changes predt/predf to not take any arguments and adds
documentation about how predicated execution works.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27982>
Tomeu Vizoso
José Roberto de Souza
Rohan Garg
Martin Roukala (né Peres)
Philipp Zabel
Mike Blumenkrantz
Connor Abbott
Samuel Pitoiset
Karol Herbst
Corentin Noël
Iago Toral Quiroga
Yonggang Luo
Yiwei Zhang
Sagar Ghuge
Caio Oliveira
Pierre-Eric Pelloux-Prayer
Leo Liu
Job Noorman