Commit Graph

166307 Commits

Author SHA1 Message Date
SoroushIMG 4c647c9e25 zink: only save frag const buffers when used by blit
fixes upload manager constant buffer leak.
zink only needs to save the const buffer for stencil fallback blits.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21134>
2023-02-06 14:47:47 +00:00
Rhys Perry c68f9ed020 radv/llvm: use the ring_offsets shader arg
Besides being nicer, this also fixes load_sample_positions_amd with LLVM.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
2023-02-06 14:25:16 +00:00
Rhys Perry be6f30a0db ac/llvm: let ring_offsets be accessed like a normal arg
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
2023-02-06 14:25:16 +00:00
Rhys Perry 24618721d3 ac: move ring_offsets to ac_shader_args
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19202>
2023-02-06 14:25:15 +00:00
Rhys Perry 10a5035c83 radv: set state.vbo_misaligned_mask_invalid in radv_bind_vs_input_state
Found by inspection. Something probably hangs because of this, but I don't
know what.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: c199a5160a ("radv: bind the VS input state for prologs created with GPL")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20913>
2023-02-06 14:05:13 +00:00
Luigi Santivetti 21f0fc65b2 pvr: add padding bytes when allocating buffer memory
We need to pad VkBuffers to ensure we don't read beyond a page boundary.

An alternative to this approach would be to allocate an additional virtual
page when binding memory to the buffer, and to map this to the first
physical address, so both the first and last virtual page point to the same
physical location. This would be less expensive in terms of memory usage,
but more complex and invasive, hence the simpler approach has been taken
for now.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21101>
2023-02-06 11:18:38 +00:00
Karmjit Mahil 4e75e1bfec pvr: Set SPMSCRATCHBUFFER flag.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
2023-02-06 10:47:38 +00:00
Karmjit Mahil ad8c0878b4 pvr: Update comment about ZS and MSAA buffers for pvrsrvkm submission.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
2023-02-06 10:47:38 +00:00
Karmjit Mahil 3457f8083a pvr: Acquire scratch buffer on framebuffer creation.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
2023-02-06 10:47:38 +00:00
Karmjit Mahil ad9c61c292 pvr: Add SPM scratch buffer infrastructure.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
2023-02-06 10:47:38 +00:00
Lionel Landwerlin e37f458207 intel/ds: track end of pipe bits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Lionel Landwerlin a242500eb4 anv: rename a few internal functions to highlight gfx use
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Lionel Landwerlin 6a23b18730 anv: rename RT pipeline function helper
Making it clear this is intended for RT pipelines only.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Lionel Landwerlin fd7debc8bb intel/fs: make alpha_to_coverage a tristate
That way in some cases we can do this dynamically.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand f3969e2413 intel/fs: Rework dynamic coarse handling
Use 2 flags for PI & RT messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand 964b878986 intel/fs: Break out yet another FB write helper
This new helper, do_emit_fb_writes() does the actual walk over all the
render targets to emit each of the different FB writes.  We want this in
a helper because we're about to go a bit crazy with coarse.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand 9c658b1fc8 intel/fs/validate: Assert SEND [extended] descriptors are uniform
This is required by code-gen since it generates a 1-wide OR and it'll
blow up if the register width > 1.  It's also way better than the "your
register is the wrong size" assert you get from the more generic
validation check.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand 949b42c4dc intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state
This allows us to communicate to the back-end that we don't actually
know if the framebuffer is multisampled or not.  No drivers set anything
but ALWAYS/NEVER and we still have a few ALWAYS/NEVER assumptions but
those should be asserted.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand 5644011f06 intel/compiler: Convert wm_prog_key::persample_interp to a tri-state
This allows for the possibility that we may not know at compile time if
sample shading is enabled through the API.  While we're here, also
document exactly what this bit means so we don't confuse ourselves.

v2: Fixup coarse pixel values (Lionel)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand d8dfd153c5 intel/fs: Make per-sample and coarse dispatch tri-state
Whenever one of them is BRW_SOMETIMES, we depend on dynamic flag pushed
in as a push constant.  In this case, we have to often have to do the
calculation both ways and SEL the result.  It's a bit more code but
decouples MSAA from the shader key.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:18 +00:00
Jason Ekstrand 43ca7f4178 intel/compiler: Convert brw_wm_aa_enable to brw_sometimes
There are other cases where we want a tri-state logic like this.  May as
well have one enum for all the cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Jason Ekstrand 5d1c538449 intel/fs: Return early in a couple builtin setup helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Jason Ekstrand 714a291673 intel/compiler: Use SHADER_OPCODE_SEND for PI messages
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Jason Ekstrand 9c62e0c77d nir: Remove nir_lower_io_force_sample_interpolation
It's no longer used.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Jason Ekstrand d25e5310bc intel/nir: Lower barycentrics to per-sample in a dedicated pass
This is more similar to what we do for single-sample and it should be
more clear going forward once our lowering gets more complex.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Jason Ekstrand 991d546102 intel/compiler: Document wm_prog_key::persample_interp
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
2023-02-06 09:12:17 +00:00
Marek Olšák 71a6b53192 amd: don't hardcode real VGPR allocation granularity on gfx10.3 and gfx11
That's how it really works.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:58 -05:00
Marek Olšák e673bb4ae4 amd,util: fix how lod bias is converted to fixed-point
according to internal docs

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Marek Olšák fb5d31c3dd amd/surface: clean up is_dcc_supported_by_L2
no functional change, though this removes "<=" for navi10, which was
never true in the "<" case

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Marek Olšák 70d228188a radeonsi: clean up si_set_mutable_tex_desc_fields
- sink code into existing branches
- remove unnecessary clearing of fields
- no functional change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Marek Olšák 4f246f27b1 amd: define new SET_*_REG_PAIRS packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Marek Olšák 97f30fc65f radeonsi/gfx11: don't add alpha to mrt0 format for A2C if exporting via mrtz
If alpha-to-coverage is exported via mrtz, don't upgrade the mrt0 format
to one with an alpha channel.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Marek Olšák 0f81224e70 radeonsi/gfx11: don't add mrt0 export for alpha-to-coverage if mrtz is present
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
2023-02-05 23:23:45 -05:00
Alyssa Rosenzweig 6b97f396e6 nir/lower_clip: Only emit 1 discard
If we have multiple clip planes, rather than emit multiple discards we can just
OR together the discard criteria. Then a nir_opt_algebraic rule kicks in to
optimize out the flt/.../flt/ior/.../ior into fmin/.../fmin/flt, generating
much less code at the end.

Written while debugging an unrelated issue with the clip lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21103>
2023-02-06 02:50:20 +00:00
Mike Blumenkrantz b481e3ae57 zink: conditionally enable PIPE_CAP_NULL_TEXTURES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
2023-02-05 13:32:02 +00:00
Mike Blumenkrantz 8b000ebbb5 radeonsi: set PIPE_CAP_NULL_TEXTURES
fixes #8163

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
2023-02-05 13:32:02 +00:00
Mike Blumenkrantz 2127287d4d gallium: add PIPE_CAP_NULL_TEXTURES
this allows drivers to indicate that they support sampling from null
textures instead of using fallback textures

for now, this is only used for depth-based fallback textures

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
2023-02-05 13:32:02 +00:00
Konstantin Seurer 7f98fcae52 radv: Scalarize global IO with LLVM enabled
Fixes the "atomic store operand must have integer, pointer, or floating point type!" error with RADV_DEBUG=llvm,checkir.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20840>
2023-02-05 12:40:25 +00:00
Konstantin Seurer 10ac51a52b ac/llvm: Fix validation error with global io
Fixes: afd645f057 ("ac/llvm: remove LLVMBuildGEP usages")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
2023-02-05 12:16:05 +00:00
Konstantin Seurer 55175cd13c radv/llvm: Use the shader names as module name
This makes it easier to identify which (if any) shaders fail validation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
2023-02-05 12:16:05 +00:00
Konstantin Seurer 877e150ec8 radv/rq: Use 16 stack entries if there is only one ray query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21120>
2023-02-05 11:51:42 +00:00
Asahi Lina 4ca4a05627 meson: Fix Asahi build on macOS
!19950 introduced a dependency between NIR and Vulkan headers, and the
Vulkan headers try to include X11 headers we cannot find on macOS.

Disable this (we have no plans for Vulkan on the macOS testing platform
anyway).

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21059>
2023-02-05 09:15:48 +00:00
Alyssa Rosenzweig bfa7ec0aa0 agx: Don't scalarize preambles in NIR
Scalarizing preambles in NIR isn't really necessary, we can do it more
efficiently in the backend. This makes the final NIR a lot less annoying to
read; the backend IR was already nice to read thanks to all the scalarized moves
being copypropped. Plus, this is a lot simpler.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
2023-02-05 08:53:29 +00:00
Alyssa Rosenzweig 7edd42cbc0 agx: Lower uniform sources with a dedicated pass
Move the decision of "can I copyprop this uniform?" from copyprop to a
standalone lowering pass. This is more straightforward and will enable the next
patch. This has the side effect of sinking load_preamble instructions, for a
nice reduction in register pressure. Instruction count increase is from
rematerializing some moves, which should be more than balanced out by the
reduced register pressure.

total instructions in shared programs: 1523285 -> 1523317 (<.01%)
instructions in affected programs: 1148 -> 1180 (2.79%)
helped: 0
HURT: 13
HURT stats (abs)   min: 1.0 max: 4.0 x̄: 2.46 x̃: 2
HURT stats (rel)   min: 0.69% max: 7.69% x̄: 3.65% x̃: 2.61%
95% mean confidence interval for instructions value: 1.78 3.14
95% mean confidence interval for instructions %-change: 2.16% 5.15%
Instructions are HURT.

total bytes in shared programs: 10444532 -> 10444724 (<.01%)
bytes in affected programs: 7386 -> 7578 (2.60%)
helped: 0
HURT: 13
HURT stats (abs)   min: 6.0 max: 24.0 x̄: 14.77 x̃: 12
HURT stats (rel)   min: 0.63% max: 7.14% x̄: 3.40% x̃: 2.48%
95% mean confidence interval for bytes value: 10.68 18.85
95% mean confidence interval for bytes %-change: 2.02% 4.78%
Bytes are HURT.

total halfregs in shared programs: 419444 -> 416434 (-0.72%)
halfregs in affected programs: 27080 -> 24070 (-11.12%)
helped: 634
HURT: 0
helped stats (abs) min: 1.0 max: 30.0 x̄: 4.75 x̃: 2
helped stats (rel) min: 2.90% max: 54.55% x̄: 13.13% x̃: 8.51%
95% mean confidence interval for halfregs value: -5.08 -4.41
95% mean confidence interval for halfregs %-change: -14.03% -12.23%
Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
2023-02-05 08:53:29 +00:00
Alyssa Rosenzweig e44a53f5dc agx: Run DCE twice
Needed to combine fsat with vectors due to nir_lower_blend changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
2023-02-05 08:53:29 +00:00
Alyssa Rosenzweig cd8b5427c7 agx: Allow uniform sources on phis
The parallel copy lowering has been able to handle uniform sources since 98f0ebf264 ("agx:
Pass agx_index to agx_copy"), and uniform sources work fine with phis. It's not
super common but there's no need to restrict them. This is a small instruction
count win and will greatly simplify the lowering later in this series.

total instructions in shared programs: 1523806 -> 1523285 (-0.03%)
instructions in affected programs: 17088 -> 16567 (-3.05%)
helped: 38
HURT: 1
helped stats (abs) min: 1.0 max: 44.0 x̄: 13.95 x̃: 7
helped stats (rel) min: 0.42% max: 18.64% x̄: 4.73% x̃: 1.26%
HURT stats (abs)   min: 9.0 max: 9.0 x̄: 9.00 x̃: 9
HURT stats (rel)   min: 8.57% max: 8.57% x̄: 8.57% x̃: 8.57%
95% mean confidence interval for instructions value: -17.95 -8.77
95% mean confidence interval for instructions %-change: -6.35% -2.43%
Instructions are helped.

total bytes in shared programs: 10447658 -> 10444532 (-0.03%)
bytes in affected programs: 118850 -> 115724 (-2.63%)
helped: 38
HURT: 1
helped stats (abs) min: 6.0 max: 264.0 x̄: 83.68 x̃: 45
helped stats (rel) min: 0.36% max: 16.51% x̄: 4.14% x̃: 1.09%
HURT stats (abs)   min: 54.0 max: 54.0 x̄: 54.00 x̃: 54
HURT stats (rel)   min: 7.30% max: 7.30% x̄: 7.30% x̃: 7.30%
95% mean confidence interval for bytes value: -107.68 -52.62
95% mean confidence interval for bytes %-change: -5.55% -2.13%
Bytes are helped.

total halfregs in shared programs: 419446 -> 419444 (<.01%)
halfregs in affected programs: 29 -> 27 (-6.90%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
2023-02-05 08:53:29 +00:00
Luc Ma abe6d750e5 xlib: fix glXDestroyContext in Gallium frontends
when glx is built with -Dglx=xlib, the mishandle in
glXDestroyContext causes glmark2 to exit unexpectedly.

Error: Glmark2 needs OpenGL(ES) version >= 2.0 to run (but version string is: '(null)')!
Error: Failed to add vertex shader from file None:
Error:   Failed to create the new program
[build] <default>: Set up failed

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3985

Signed-off-by: Luc Ma <luc@sietium.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21067>
2023-02-04 22:25:09 +00:00
SoroushIMG 8f928a95e1 zink: fix cap check for arb sparse texture2
arb_sparse_texture2 also enables multisampled sparse textures.
bring back the check for msaa support.

fixes #8229

Fixes: 4f8ba2b9aa ("zink: fix sparse residency query and minLOD feature checks")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21121>
2023-02-04 18:05:48 +00:00
Alyssa Rosenzweig 93db6094a1 nir/print: Pretty-print color0/1_interp
These are an enum. Furthermore, their 0 state is INTERP_MODE_NONE which we
shouldn't bother printing at all.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
2023-02-04 17:26:30 +00:00
Alyssa Rosenzweig b235be1fd4 nir/print: Pretty-print I/O semantic locations
Instead of printing the raw location number, which is pretty hard to interpret,
let's print the name of the location. Example output:

   vec4 16 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=0,
   component=0, dest_type=float16 /*144*/, io location=VARYING_SLOT_VAR0 slots=1
   mediump /*8388768*/)

One of the "regressions" from moving to purely lowered I/O with all variables
removed is a lack of debuggability, since otherwise these location strings don't
show up anywhere in the printed shader! By contrast this should make the lowered
I/O nice to read like the early I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
2023-02-04 17:26:30 +00:00