Commit Graph

178660 Commits

Author SHA1 Message Date
Martin Roukala (né Peres) 98bc20041c ci: make B2C_JOB_VOLUME_EXCLUSIONS to all .b2c-test jobs
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25429>
2023-10-02 14:50:27 +00:00
Georg Lehmann 79b767f4c0 aco: remove -0.0 for 32 bit fsign with mul_legacy/omod when denorms are flushed
v_mul_legacy_f32 and omod return +0.0 if any operand is +0.0/-0.0.

Foz-DB Navi21:
Totals from 4289 (5.60% of 76572) affected shaders:
Instrs: 8100571 -> 8099319 (-0.02%); split: -0.02%, +0.00%
CodeSize: 43433200 -> 43435088 (+0.00%); split: -0.01%, +0.01%
Latency: 88151566 -> 88147232 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 22966705 -> 22965192 (-0.01%); split: -0.01%, +0.00%
VClause: 190010 -> 190009 (-0.00%)
SClause: 269697 -> 269689 (-0.00%)
Copies: 687294 -> 687296 (+0.00%); split: -0.00%, +0.00%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>
2023-10-02 14:02:49 +00:00
Georg Lehmann 9508cadadb aco/optimizer: copy propagate to output modifier instructions
Foz-DB Navi21:
Totals from 847 (1.11% of 76572) affected shaders:
Instrs: 2331245 -> 2330335 (-0.04%); split: -0.04%, +0.00%
CodeSize: 12451040 -> 12451736 (+0.01%); split: -0.00%, +0.01%
Latency: 26230953 -> 26229153 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 6297802 -> 6296788 (-0.02%); split: -0.02%, +0.00%
VClause: 64527 -> 64528 (+0.00%); split: -0.00%, +0.01%
SClause: 73150 -> 73121 (-0.04%); split: -0.06%, +0.02%
Copies: 180083 -> 179172 (-0.51%); split: -0.53%, +0.02%
PreSGPRs: 62311 -> 62316 (+0.01%)
PreVGPRs: 51720 -> 51710 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>
2023-10-02 14:02:49 +00:00
Georg Lehmann 89f3a5ea37 aco/optimizer: check if we can use omod before labeling it
Allows to use omod for v_mul_legacy_f32 regardless of signedZeroInfNaNPreserve

Foz-DB Navi21:
Totals from 15 (0.02% of 76572) affected shaders:
Instrs: 20131 -> 20113 (-0.09%)
CodeSize: 107100 -> 107144 (+0.04%)
Latency: 400789 -> 400470 (-0.08%)
InvThroughput: 62342 -> 62278 (-0.10%)
Copies: 1194 -> 1176 (-1.51%)
PreVGPRs: 787 -> 785 (-0.25%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25347>
2023-10-02 14:02:49 +00:00
Samuel Pitoiset d3033974ee radv/ci: update list of flakes for NAVI10/VEGA10
This one is fixed since CTS 1.3.6.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25505>
2023-10-02 14:44:58 +02:00
Samuel Pitoiset 387dc05a61 radv/ci: update list of expected failures on PITCAIRN
This one is fixed since CTS 1.3.6.3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25505>
2023-10-02 14:44:35 +02:00
Samuel Pitoiset b01e874234 radv: fix alignment of DGC command buffers
Otherwise, DGC command buffers might not be correctly aligned.

This fixes a regression with the vkd3d-proton DGC tests.

Fixes: 4f660f9937 ("ac/gpu_info: pad IBs according to ib_size_alignment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25500>
2023-10-02 12:21:44 +00:00
Tapani Pälli 1c4d57568a intel/genxml: remove HDC from gen11.xml, it is not available
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>
2023-10-02 12:05:54 +00:00
Tapani Pälli a49ff4e024 iris: HDC flush is available only for GFX_VER 12+
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>
2023-10-02 12:05:54 +00:00
Tapani Pälli 99d3d76646 anv: HDC flush is available only for GFX_VER 12+
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>
2023-10-02 12:05:53 +00:00
Tapani Pälli c02db0d90f iris: flush data cache when flushing HDC on GFX < 12
This matches what anv driver does.

Fixes: a969ad1d ("iris: Demote DC flush to HDC flush in cache tracker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6314
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25399>
2023-10-02 12:05:53 +00:00
Rhys Perry 558738e3c5 aco: remove zero offset optimization
This is done in nir_opt_constant_folding now.

No fossil-db changes on navi31.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>
2023-10-02 10:11:37 +00:00
Rhys Perry 7139a78959 nir/constant_folding: remove zero texel offset
fossil-db (navi31):
Totals from 7 (0.01% of 79330) affected shaders:
Instrs: 7001 -> 6993 (-0.11%)
CodeSize: 35736 -> 35692 (-0.12%)
InvThroughput: 3232 -> 3229 (-0.09%)
Copies: 552 -> 549 (-0.54%)
PreSGPRs: 277 -> 273 (-1.44%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>
2023-10-02 10:11:37 +00:00
Rhys Perry c3a894fb47 aco: disable zero offset optimization for strict WQM coords
If we try to do this, we end up using {undef,coordx} as the coordinates
for an image_sample instruction, because we can't shrink the linear VGPR.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9767
Fixes: 859e059aa9 ("radv: use fix_derivs_in_divergent_cf")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25477>
2023-10-02 10:11:37 +00:00
Georg Lehmann 305db1af11 nir: scalarize masked_swizzle_amd created from shuffle_xor
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9901
Fixes: 0ef87f148d ("nir/lower_subgroups: Don't do multiple lowerings at once")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25468>
2023-10-02 09:01:18 +00:00
Tapani Pälli 524e8865ce iris/anv: move Wa_14018912822 as a drirc workaround
This should be toggled on only for applications that hit the issue.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9886
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25424>
2023-10-02 08:26:14 +00:00
Tapani Pälli ebe95fee21 iris: correct dst alpha blend factor in Wa_14018912822
Fixes: 0e9a26372b ("iris: implement Wa_14018912822")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25424>
2023-10-02 08:26:14 +00:00
Lionel Landwerlin 6ea2ea0bb0 anv: fix internal compute copy shader build
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9907
Fixes: 2cc5b3b1e0 ("anv: add a memcpy compute internal kernel")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25480>
2023-10-02 07:39:01 +00:00
Christian Gmeiner d48d8aefdf docs: Move isaspec out of drivers/freedreno
Lets put it under 'Developer Topics'.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25452>
2023-10-02 07:20:13 +00:00
Iago Toral Quiroga 4afbf4ad31 v3d: get rid of shader_state pointer in v3d_key
Having this pointer in the key is undesirable since it makes
copying keys difficult and error prone (as seen in previous
patches), also, it is only there for convenience and we don't
strictly need it (in fact the vulkan driver doesn't use it at
all), so let's just get rid of it so our v3d_key is fully
static.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>
2023-10-02 06:35:07 +00:00
Iago Toral Quiroga 3fb9e27a3d v3d: fix RAM shader cache
The RAM shader cache was using the v3d_key for hashes and
comparisons which is not correct. Particularly, this struct
has a void pointer where we store a reference to an uncompiled
shader with the NIR code, and that is of course not accounted
for when hashing and comparing keys, which can lead to bogus
cache hits.

This patch introduces a v3d_cache_key that has both the v3d key
and a sha1 of the uncompiled NIR. Now key hashing and comparison
is done on the static part of the v3d key (that is, excluding the
uncompiled shader pointer, which may be invalid in the cache if
the original shader was deleted) and taking the sha1 from the
uncompiled shader. This also makes sure the shader key we store
in the cache has a NULL shader_state pointer to make it more
clear that this field may not be used at all for caching purposes.

This fixes GPU hangs with some OpenCL tests (through Rusticl)
caused by incorrect RAM cache hits.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>
2023-10-02 06:35:07 +00:00
Iago Toral Quiroga 8a4bd328cf v3d: use pre-computed shader sha1 for disk cache
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>
2023-10-02 06:35:06 +00:00
Iago Toral Quiroga 0ed36b524c v3d: compute nir sha1 for uncompiled shader state
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>
2023-10-02 06:35:06 +00:00
Iago Toral Quiroga adc63d2503 broadcom/compiler: add a couple of shader key helpers
Our shader key includes a void pointer that we can't just memcmp,
so add helpers that allow us toget the 'static' portion and size
of a key. We will use this to fix up the shader cache in v3d in
a later patch.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25418>
2023-10-02 06:35:06 +00:00
Sergi Blanch Torne ccd3e68146 ci: disable Collabora's LAVA lab for maintance
This is to inform you of some planned downtime in the LAVA lab as follows:
* Start: 2023-10-02 08:00 BST (07:00 UTC)
* End: 2023-10-02 12:00 BST (11:00 UTC)

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25368>
2023-10-02 07:42:08 +02:00
Martin Roukala (né Peres) b1156507ed ci/vkcts-navi21: mark more of the RT handles checks as flakes
We keep hitting more and more of them, so let's be more inclusive.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25495>
2023-10-02 03:08:11 +00:00
Martin Roukala (né Peres) a7ed839490 ci/vkcts-vangogh: mark dEQP-VK.dynamic_rendering.primary_cmd_buff.basic.* as flake
This mirrors what we did on navi21, as there are just too many of these tests.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25495>
2023-10-02 03:08:11 +00:00
Janne Grunau dbe2230408 asahi: decode: Fix uint64_t format modifiers in agxdecode_stateful()
Fixes i386 build.

Fixes: acd5ed0451 ("asahi: decode: Implement VDM call/ret")
Signed-off-by: Janne Grunau <j@jannau.net>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig d99ed6d66d asahi: Handle layered background programs
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 3715586580 asahi: Generate layered EOT programs
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig c87095e518 asahi: Use a 2D Array texture for array render targets
Fixes KHR-GLES31.core.geometry_shader.layered_framebuffer.blending_support with
eMRT forced.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 87a7b239e1 asahi: Write to cubes/etc attachments as 2D array
To reduce shader variants, the tilebuffer lowering code does not know the
actual texture targets of the spilled render targets, only whether they are
layered or not. As such, all layered targets (3D, cube map, etc) get written out
uniformly as 2D Arrays. For that to work, the driver needs to do the
corresponding transform.

Regular imageStore() instructions are not affected by any of this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 0cbecc1ad1 asahi: Predicate layer ID reads
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig e2a0d64d52 asahi: Add pass to predicate layer ID reads
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig e518c92d26 asahi: Assume LAYER is flat-shaded
It can't be anything else, this makes sure the varyings are sorted properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 68437eb0ba asahi: Account for layering for attachment views
Do not force a single-layer view, use an actual array attachment when there are
multiple layers, since this corresponds to a layered framebuffer that will write
to an array with the eMRT path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 9dc87a00fd asahi: Expose VS_LAYER_VIEWPORT behind a flag
We can't technically expose the extension without a higher GL version, but the
implemented subset should work and this lets us test with piglit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 2396d3fe62 asahi: Use layered layouts
For correct eMRT code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 8a48af4f8f agx/lower_tilebuffer: Support spilled layered RTs
If we spill render targets with a layered framebuffer, our spilled targets are
assumed to be 2D Arrays (in general). We need to use arrayed image operations to
load/store from these. The layer is given by the layer as read in the fragemnt
shader. This handles the eMRT portion of layered rendering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig 041451b655 agx/tilebuffer: Support layered layouts
Just add a flag for it. We don't care about the actual # of layers when
calculating the layout, only the boolean fact of being layered or not. The
reason we need this at all is because the eMRT implementation needs to
account for layering and that is only keyed off the tilebuffer layout.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:37:55 -04:00
Alyssa Rosenzweig b252630604 agx: Support packed layered rendering writes
With the new pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig 4a954dff07 asahi,agx: Select layered rendering outputs
These 2 are together

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig 88fd76d378 asahi: Add helper to get layer id in internal program
For background/EOT only.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig 7d94f2ee49 agx: Add pass to lower layer ID writes
The hardware needs the layer ID and the viewport index packed together. That
consumes an entire varying slot, if we want those available in the frag shader
we need a separate slot. Add a pass to insert the extra packed write.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig 175819eec6 agx: Handle layered block image stores
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig c3a208d6d9 agx: Pack block image store dim correctly
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig da0da5d6f8 agx/nir_lower_texture: Allow disabling layer clamping
For background program with layered.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig 10b9c2fa36 nir: Support arrays in block_image_store_agx
For layered rendering, runs once per layer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:12 -04:00
Alyssa Rosenzweig f4042afd57 nir: Add layer_id_written_agx sysval
We'll implement layer ID reads in the frag shader with a varying read, but if
the VS doesn't write the varying we need to return 0 per the spec. Add a sysval
to detect that case so we can handle it at runtime without keys.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00
Alyssa Rosenzweig d83d24e96a agx: Insert jmp_exec_none instructions
With the exception of the backwards branch for loops, all the control flow we
insert during instruction selection just predicates instructions rather than
actually jumping around. That means, for example, we execute both sides of the
if even for a uniform condition! That's inefficient. The solution is insert
jmp_exec_none instructions after control flow in order to skip unexecuted
regions, which is much faster than predicating them out. However, jmp_exec_none
is costly in itself, so we need to use a heuristic to determine when it's
actually beneficial.

This uses a very simple heuristic for this purpose. However, it is a massive
performance speed-up for Dolphin uber shaders: 39fps -> 67fps at 2x resolution.
Nearly a doubling of performance!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-01 12:32:11 -04:00