Commit Graph

96643 Commits

Author SHA1 Message Date
Iago Toral Quiroga 5ec21eb1a0 i965/tes: account for the fact that dvec3/4 inputs take two slots
When computing the total size of the URB for tessellation evaluation
inputs we were not accounting for this, and instead we were always
assuming that each input would take a single vec4 slot, which could
lead to computing a smaller read size than required. Specifically, this
is a problem when the last input is a dvec3/4 such that its XY components
are stored in the the second half of a payload register (which can happen
if the offset for the input in the URB is not 64-bit aligned because
there are 32-bit inputs mixed in) and the ZW components in the
first half of the next, as in this case we would fail to account for the
extra slot required for the ZW components.

Fixes (requires another fix in CTS currently in review):
KHR-GL45.enhanced_layouts.varying_locations
KHR-GL45.enhanced_layouts.varying_array_locations

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-10-10 08:59:54 +02:00
Tapani Pälli 63e6db18c5 anv: fix null pointer dereference
CID: 1419033

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-10 08:17:44 +03:00
Dave Airlie 4adc456580 radv: export KHR_relaxed_block_layout
This seems to pass all the cts tests it enables.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-10 13:22:44 +10:00
Ilia Mirkin ce6da2a026 nv50/ir: fix 64-bit integer shifts
TGSI was adjusted to always pass in 64-bit integers but nouveau was left
with the old semantics. Update to the new thing.

Fixes: d10fbe5159 (st/glsl_to_tgsi: fix 64-bit integer bit shifts)
Reported-by: Karol Herbst <karolherbst@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-09 20:42:59 -04:00
Lionel Landwerlin 8ee6828df7 i965: silence coverity warning
Also makes this statement a bit clearer.

CID: 1418920
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Antia Puentes <apuentes@igalia.com>
2017-10-10 00:56:01 +01:00
Józef Kucia 91ba331ef4 anv: Do not assert() on VK_ATTACHMENT_UNUSED
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-09 16:28:43 -07:00
Józef Kucia e0acb630a5 spirv: Fix SpvOpAtomicISub
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
2017-10-09 16:28:11 -07:00
Timothy Arceri 7a7fb90af7 glsl: tidy up IR after loop unrolling
c7affbf687 enabled GLSLOptimizeConservatively on some
drivers. The idea was to speed up compile times by running
the GLSL IR passes only once each time do_common_optimization()
is called. However loop unrolling can create a big mess and
with large loops can actually case compile times to increase
significantly due to a bunch of redundant if statements being
propagated to other IRs.

Here we make sure to clean things up before moving on.

There was no measureable difference in shader-db compile times,
but it makes compile times of some piglit tests go from a couple
of seconds to basically instant.

The shader-db results seemed positive also:

Totals:
SGPRS: 2829456 -> 2828376 (-0.04 %)
VGPRS: 1720793 -> 1721457 (0.04 %)
Spilled SGPRs: 7707 -> 7707 (0.00 %)
Spilled VGPRs: 33 -> 33 (0.00 %)
Private memory VGPRs: 3140 -> 2060 (-34.39 %)
Scratch size: 3308 -> 2180 (-34.10 %) dwords per thread
Code Size: 79441464 -> 79214616 (-0.29 %) bytes
LDS: 436 -> 436 (0.00 %) blocks
Max Waves: 558670 -> 558571 (-0.02 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-10-10 10:05:37 +11:00
Timothy Arceri 646621c66d glsl: make loop unrolling more like the nir unrolling path
The old code assumed that loop terminators will always be at
the start of the loop, resulting in otherwise unrollable
loops not being unrolled at all. For example the current
code would unroll:

  int j = 0;
  do {
     if (j > 5)
        break;

     ... do stuff ...

     j++;
  } while (j < 4);

But would fail to unroll the following as no iteration limit was
calculated because it failed to find the terminator:

  int j = 0;
  do {
     ... do stuff ...

     j++;
  } while (j < 4);

Also we would fail to unroll the following as we ended up
calculating the iteration limit as 6 rather than 4. The unroll
code then assumed we had 3 terminators rather the 2 as it
wasn't able to determine that "if (j > 5)" was redundant.

  int j = 0;
  do {
     if (j > 5)
        break;

     ... do stuff ...

     if (bool(i))
        break;

     j++;
  } while (j < 4);

This patch changes this pass to be more like the NIR unrolling pass.
With this change we handle loop terminators correctly and also
handle cases where the terminators have instructions in their
branches other than a break.

V2:
- fixed regression where loops with a break in else were never
  unrolled in v1.
- fixed confusing/wrong naming of bools in complex unrolling.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-10-10 10:05:37 +11:00
Timothy Arceri d24e16fe1f glsl: check if induction var incremented before use in terminator
do-while loops can increment the starting value before the
condition is checked. e.g.

  do {
    ndx++;
  } while (ndx < 3);

This commit changes the code to detect this and reduces the
iteration count by 1 if found.

V2: fix terminator spelling

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-10-10 10:05:37 +11:00
Timothy Arceri ab23b759f2 glsl: don't drop instructions from unreachable terminators continue branch
These instructions will be executed on every iteration of the loop
we cannot drop them.

V2:
- move removal of unreachable terminators from the terminator list
  to the same place they are removed from the IR as suggested by
  Nicolai.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-10-10 10:05:37 +11:00
Dylan Baker c63ce5c95d travis: Add a travis profile for meson dri drivers
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
2017-10-09 13:55:12 -07:00
Dylan Baker 68c91264eb travis: don't run ninja test for meson
This pulls in tons of extra dependencies because the tests are not
properly guarded.

v2: - Put this patch before the one that adds a loader/dri test for
      meson

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
2017-10-09 13:54:46 -07:00
Dylan Baker c2cd5801cd meson: build classic swrast
This adds support for building the classic swrast implementation. This
driver has been tested with glxinfo and glxgears.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:44 -07:00
Dylan Baker 816bf7d164 meson: build gbm
This doesn't include egl support, just dri support.

v2: - when gbm is set to 'auto', only build if a dri driver is also
      enabled
    - Fix conditional to check for x11 modules with vulkan as well as
      with dri drivers
v3: - Set pkgconfig libraries.private value

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:44 -07:00
Dylan Baker db9788420d meson: Add support for configuring dri drivers directory.
v2: - drop with_ from dri_drivers_path variable (Eric A)
v3: - Move HAVE_X11_PLATFORM to the proper patch (Eric A)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:44 -07:00
Dylan Baker a47c525f32 meson: build glx
This gets GLX and the loader building. The resulting GLX and i965 have
been tested on piglit and seem to work fine. This patch leaves a lot of
todo's in it's wake, GLX is quite complicated, and the build options
involved are many, and the goal at the moment is to get dri and gallium
drivers building.

v2: - fix typo "vaule" -> "value"
    - put the not on the correct element of the conditional
    - Put correct description of dri3 option in this patch not the next
      one (Eric A)
    - fix non glvnd version (Eric A)
    - build glx tests
    - move loader include variables to this patch (Eric A)
v3: - set the version correctly for GL_LIB_NAME in libglx
v4: - set pkgconfig private fields

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:44 -07:00
Dylan Baker 3218056e0e meson: Build i965 and dri stack
This gets pretty much the entire classic tree building, as well as
i965, including the various glapis. There are some workarounds for bugs
that are fixed in meson 0.43.0, which is due out on October 8th.

I have tested this with piglit using glx.

v2: - fix typo "vaule" -> "value"
    - use gtest dep instead of linking to libgtest (rebase error)
    - use gtest dep instead of linking against libgtest (rebase error)
    - copy the megadriver, then create hard links from that, then delete
      the megadriver. This matches the behavior of the autotools build.
      (Eric A)
    - Use host_machine instead of target_machine (Eric A)
    - Put a comment in the right place (Eric A)
    - Don't have two variables for the same information (Eric A)
    - Put pre_args at top of file in this patch (Eric A)
    - Fix glx generators in this patch instead of next (Eric A)
    - Remove -DMESON hack (Eric A)
    - add sha1_h to mesa in this patch (Eric A)
    - Put generators in loops when possible to reduce code in
      mapi/glapi/gen (Eric A)
v3: - put HAVE_X11_PLATFORM in this patch

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:44 -07:00
Dylan Baker 86eb09a136 meson: de-tabularize meson_options.txt
This ends up being unworkable as more options get added, and with
description wrapped onto a new line it doesn't improve readability
anyway.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:43 -07:00
Dylan Baker 97aea7d507 meson: only require libelf if building radv
And add a todo about clover, r600, and radeonsi, which also need libelf.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:43 -07:00
Dylan Baker 001b65a899 meson: add nir_linking_helpers.c to libnir
This was missed in a rebase, and doesn't affect radv or anv, only i965.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:43 -07:00
Dylan Baker fc48ad2427 make: Fix test to be meson compatible
This has the same problem as the previous commit, generated headers and
hardcoded paths.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:43 -07:00
Dylan Baker 1b1bb6ee10 make: Don't traverse backwards through include directories.
Traversing back through includes is bad idea and should be avoided.
In the case here - indirect_size.h is located in the build directory
$(top_builddir)/src/glx/.

v3: - Update commit message with message provided by Emil

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:42:43 -07:00
Dylan Baker e5866af123 editorconfig: Add meson configuration
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-09 13:40:50 -07:00
Christian Gmeiner 148604fe75 etnaviv: call util_query_clear_result(..) in the generic layer
Saves us from calling util_query_clear_result(..) in every query
type implementation.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-09 22:19:47 +02:00
Christian Gmeiner b22bacc6cf etnaviv: push query active handling into generic layer
We want the same active handling for every query type. So lets
handle it in the generic layer.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-By: Wladimir J. van der Laan <laanwj@gmail.com>
2017-10-09 22:19:31 +02:00
Dave Airlie bee61d16c8 r600: drop a bunch of post-cayman code. (v2)
Now that Marek has split the two drivers apart, drop a bunch
of unnecessary code from the r600 half. There is probably a bunch
more hiding in the video code.

No piglit regressions on caicos.

v2: fix HAVE_LLVM protected code
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-10 06:08:42 +10:00
Marek Olšák 7b697c8b78 amd: move r600d_common.h into r600g
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:06 +02:00
Marek Olšák 76997e9133 radeonsi: shrink r600d_common.h and stop using it
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:05 +02:00
Marek Olšák 0ecf9b90ef radeonsi: import cayman_msaa.c from drivers/radeon
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:04 +02:00
Marek Olšák 345f04ed92 radeonsi: remove r600_emit_reloc
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:02 +02:00
Marek Olšák da61946cb1 radeonsi: merge si_set_streamout_targets with si_common_set_streamout_targets
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:27:00 +02:00
Marek Olšák a86c9328ce radeonsi: add si_so_target_reference
The src type is different on purpose.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:26:58 +02:00
Marek Olšák 65f2e33500 radeonsi: import r600_streamout from drivers/radeon
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:26:55 +02:00
Marek Olšák ed7f27ded8 radeonsi: add performance thresholds for CP DMA, decrease it for clears
The first one isn't used yet.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:24:21 +02:00
Marek Olšák 8e969cce38 radeonsi: disable primitive binning on Vega10 (v2)
Our driver implementation is known to decrease performance for some tests,
but we don't know if any apps and benchmarks (e.g. those tested by Phoronix)
are affected. This disables the feature just to be safe.

Set this to enable partial primitive binning:
    R600_DEBUG=dpbb
Set this to enable full primitive binning:
    R600_DEBUG=dpbb,dfsm

v2: add new debug options

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:20:18 +02:00
Marek Olšák 3784ce9782 radeonsi: enumerize DBG flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-09 16:20:16 +02:00
Marek Olšák 99fa9ccf96 drirc: whitelist glthread for Spec Ops: The Line
On i7 4790k and a 280X, there is a boost of about 10% more FPS.

Nominated by John Ettedgui.
2017-10-09 15:43:33 +02:00
Samuel Pitoiset 7824cb4b03 radv: configure VGT_VERTEX_REUSE at pipeline creation
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:19 +02:00
Samuel Pitoiset b09b43b166 radv: do not need to zero-init ds/raster states
Already done when creating the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:17 +02:00
Samuel Pitoiset d4652e7c86 radv: remove unused fields in radv_raster_state
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:06:15 +02:00
Samuel Pitoiset 6732a8369a radv: set ALPHA_TO_MASK_ENABLE at blend state init
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:05:06 +02:00
Samuel Pitoiset 5848565ee3 radv: emit PA_SU_POINT_{SIZE,MINMAX} in si_emit_config()
These registers don't change during the lifetime of the
command buffer, there is no need to re-emit them when
binding a new pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:05:04 +02:00
Samuel Pitoiset aab1537568 radv: allow launching waves out-of-order for compute
Ported from RadeonSI, and -pro seems to enable it as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-09 10:04:17 +02:00
Jason Ekstrand 6c7720ed78 anv/wsi: Allocate enough memory for the entire image
Previously, we allocated memory for image->plane[0].surface.isl.size
which is great if there is no compression.  However, on BDW, we can do
CCS_D on X-tiled images so we also have to allocate space for the
auxiliary buffer.  This fixes hangs in some of the WSI CTS tests and
should also reduce hangs in real applications.  In particular, it fixes
the dEQP-VK.wsi.*.incremental_present.* test group.

When we hand the image off to X11 or Wayland, it will ignore the CCS
entirely which is ok because we do a resolve when it's transitioned to
VK_IMAGE_LAYOUT_PRESENT_SRC_KHR.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-07 17:12:38 -07:00
Lionel Landwerlin e262845e37 anv: fix nir.h include
All over mesa we include "nir/nir.h", we should probably do the same
here. This fixes the meson build that was broken by the ycbcr series.

Thanks to Dylan for finding the issue.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: f3e91e78a3 ("anv: add nir lowering pass for ycbcr textures")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-07 22:57:50 +01:00
Jason Ekstrand 49a6fb8474 spirv: Don't warn on the ImageCubeArray capability
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-07 14:52:03 -07:00
Kenneth Graunke 37e128b9b7 mesa: make glFramebuffer* check immutable texture level bounds
When a texture is immutable, we can't tack on extra levels
after-the-fact like we could with glTexImage. So check against that
level limit and return an error if it's surpassed.

This fixes:
KHR-GL45.geometry_shader.layered_fbo.fb_texture_invalid_level_number

(Based on a patch by Ilia Mirkin.)

Reviewed-by: Antia Puentes <apuentes@igalia.com> [imirkin v2]
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-07 13:26:55 -07:00
Marek Olšák 5a47abb63e radeonsi: don't change viewport for blits, use window-space positions
The viewport state was an identity anyway.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-07 18:26:35 +02:00
Marek Olšák 76ef08f6ee radeonsi: set correct PA_SC_VPORT_ZMIN/ZMAX when viewport is disabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-10-07 18:26:35 +02:00