Commit Graph

163418 Commits

Author SHA1 Message Date
Alyssa Rosenzweig fb7257af4e asahi: Hide ctx->batch
This will make it easier to support multiple batches.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
2022-11-19 15:33:16 +00:00
Alyssa Rosenzweig 3104b1aaaf asahi: Factor out prepare_for_map
This will be expanded, let's expand in the direction of less spaghetti.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>
2022-11-19 15:33:16 +00:00
Lionel Landwerlin 9c1c1888d9 intel/fs: put scratch surface in the surface state heap
In 4ceaed7839 we made scratch surface state allocations part of the
internal heap (mapped to STATE_BASE_ADDRESS::SurfaceStateBaseAddress)
so that it doesn't uses slots in the application's expected 1M
descriptors (especially with vkd3d-proton).

But all our compiler code relies on BSS
(STATE_BASE_ADDRESS::BindlessSurfaceStateBaseAddress).

The additional issue is that there is only 26bits of surface offset
available in CS instruction (CFE_STATE, 3DSTATE_VS, etc...) for
scratch surfaces. So we need the drivers to put the scratch surfaces
in the first chunk of STATE_BASE_ADDRESS::SurfaceStateBaseAddress
(hence all the driver changes).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4ceaed7839 ("anv: split internal surface states from descriptors")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7687
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
2022-11-19 14:58:58 +00:00
Lionel Landwerlin daab161535 iris: move bindless surface state heap inside the surface state heap
We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:

   - 8Mb of surface states for scratch
   - 1Gb - 8Mb of binding tables
   - 3Gb of surface states

That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
2022-11-19 14:58:57 +00:00
Lionel Landwerlin 64f1ae4bc5 iris: prevent crash in decoder
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
2022-11-19 14:58:57 +00:00
Bas Nieuwenhuizen 1b5dc33caa radv: Convert instance bvh address to node in bvh build.
So we don't have to do it in the traversal loop. Should 2 and
instructions and a 64-bit shift, so 4/8 cycles per instance node
visit.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 208460 -> 208292 (-0.08%)
Instrs: 38276 -> 38248 (-0.07%)
Latency: 803181 -> 803142 (-0.00%)
InvThroughput: 165384 -> 165376 (-0.00%)
Copies: 4912 -> 4905 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
2022-11-19 14:24:36 +00:00
Bas Nieuwenhuizen d09ed23b9a radv: Fiddle with opaque flag positions to reduce instructions.
Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 209076 -> 208460 (-0.29%)
Instrs: 38374 -> 38276 (-0.26%)
Latency: 803899 -> 803181 (-0.09%)
InvThroughput: 165530 -> 165384 (-0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
2022-11-19 14:24:36 +00:00
Bas Nieuwenhuizen 3884210902 radv: Skip and for node_to_addr with bvh_base.
Cause the bvh base is always 64 byte aligned.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 209216 -> 209076 (-0.07%)
Instrs: 38402 -> 38374 (-0.07%)
Latency: 804537 -> 803899 (-0.08%)
InvThroughput: 165663 -> 165530 (-0.08%)
Copies: 4919 -> 4912 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
2022-11-19 14:24:36 +00:00
Bas Nieuwenhuizen 0a26975840 radv: Move ray flag compares out of the loop.
To save on and+cmp combos with VALU instructions.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 208476 -> 209216 (+0.35%)
Instrs: 38384 -> 38402 (+0.05%)
Latency: 805725 -> 804537 (-0.15%)
InvThroughput: 165906 -> 165663 (-0.15%)
Copies: 4936 -> 4919 (-0.34%)
PreSGPRs: 393 -> 430 (+9.41%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>
2022-11-19 14:24:36 +00:00
Lionel Landwerlin e2dadda35f Revert "nir/lower_shader_calls: put inserted instructions into a dummy block"
This reverts commit 35d82ecf1e.

Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
2022-11-19 10:53:18 +00:00
Lionel Landwerlin 3686d5a312 nir/lower_shader_calls: wrap only jumps rather than entire code blocks
Moving entire chunks of code into a dummy if block is causing issues
in some situations. To work around the issue that we tried to fix in
35d82ecf1e ("nir/lower_shader_calls: put inserted instructions into a
dummy block") which is that we cannot cut and past a block of
instruction that ends with a jump if there are more instruction behind
where we're going to past. We can instead just wraps the jumps into
dummy if blocks.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
2022-11-19 10:53:18 +00:00
Lionel Landwerlin 96d84e2a77 nir/lower_shader_calls: update metadata before validation
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>
2022-11-19 10:53:18 +00:00
Konstantin Seurer 6f45c98b58 radv/bvh: Adjust sah cost based on depth
Adds a cost field to radv_ir_node and uses it to model the cost of tree
depth. This improves framerates by 2% if my benchmarking is correct.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19756>
2022-11-19 10:18:50 +00:00
Ian Romanick 2ba55ec504 nir/range_analysis: Set higher default maximum for max_workgroup_count
Fixes: c2a81ebe19 ("nir: Add default unsigned upper bound configuration.")
Closes: #7676
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19835>
2022-11-19 05:40:42 +00:00
Caio Oliveira d989746e55 iris: Pass devinfo directly in iris_setup_uniforms
Instead of reaching through brw_compiler.  This will make easy
future changes on brw_compiler side.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19836>
2022-11-19 05:15:15 +00:00
Michael Skorokhodov a9602134a3 intel/compiler: Require C++17
Fixes: 6c194ddd18 ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19833>
2022-11-19 04:37:51 +00:00
Alyssa Rosenzweig 11a607dbc8 asahi: Don't support 16-bit vertex attributes
Currently broken, let vbuf deal with it. "Fixes" sysprof.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig 9dddbfeaef asahi: Fix logic ops
Need to set colour mask correctly. Fixes spec@!opengl 1.0@gl-1.0-logicop@GL_AND,
at least the non-MSAA portion.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig a22ed99906 asahi: Restrict rendering to what we support
Noticed with Kodi that tries to use rgb10a2.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig 37617ab09e asahi: Don't validate WSI (twiddled) strides
These are made up and won't necessarily be aligned.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig f328207475 asahi: Split out agx_usc.h into a common file
So the tilebuffer helpers can build the "shared" USC word. Also because Ella
will probably want to use these O:)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig 8be506039d asahi: Note some magic bits used with memoryless RTs
Obviously there can't *actually* be memoryless render targets, because
how would partial renders work? The control stream with memoryless looks
like everything would if it went to memory (e.g. full 2D MSAA
attachments for the partial loads/stores even if only a resolved
2D image for the final store). Except the memoryless attachments all
load from the same address 0xeeee0000. Clearly that's not actually what
happens, so what gives? Unclear... but I see the magic bits mentioned
here set, and I assume there are some firmware (or kernel) shenanigans
used to JIT allocate the backing storage for partial renders.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig 3fa87e47d5 asahi: Identify "Sample mask after depth/stencil" bit
Corresponds to Metal [[sample_mask,post_depth_coverage]].

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:11 +00:00
Alyssa Rosenzweig ff616099ce asahi: Identify the pass type enum
Via PowerVR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 2e6369f5f6 asahi: Identify PBE sample count
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 1f0edc0158 asahi: Identify Dimension for Render Target
Metal uses when rendering to multisampled 2D.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 016a699fa9 asahi: Fix agx_set_framebuffer_state for MRT
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 7e662320aa asahi: Set data_valid for the correct level
By inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 9c52001a1d asahi: Implement stencil texturing
Stencil texturing is easy: S8_UINT is textured like R8_UINT (with a
little swizzle fixup), and stencil is always S8_UINT thanks to
u_transfer_helper. So we just need to do some fixups to make
u_transfer_helper's seperate_stencil work and everything will work out.

Passes dEQP-GLES31.functional.stencil_texturing.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 1ffbd53aa2 asahi: Add internal formats for RGB10A2
We need to use I16 as the interchange format here. Fixes:

   dEQP-GLES3.functional.fragment_out.basic.uint.rgb10_a2ui*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig efb5aef935 asahi: Implement perf_debug
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig c8e520985b asahi: Free the scanout resource
Fixes memory leaks with renderonly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 6a12d793d8 agx: Handle collects in backwards isel
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 3b9d271646 agx: Assert more invariants in RA
Was helpful for debugging.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig c2159ce9e4 agx: Validate part of SSA form
To debug backend pass problems.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 1110fcccc2 agx: Split off NIR preprocessing from compiling
So we can specialize after lowering I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 972354b5fd agx: Handle scalar texture destinations
Fixes dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2dshadow_fragment.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig a92fb4f38c agx: Don't depend on GenXML
Separation of concerns, unused #include.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Alyssa Rosenzweig 3789dba5f6 agx: Lower packs/unpacks and bitfields
Needed for GLES3. These could be optimized.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-19 04:27:10 +00:00
Yonggang Luo 94886a2975 util: Move src/gallium/include/pipe/p_format.h to src/util/format/u_formats.h
Because p_format.h shared between vulkan drivers and opengl drivers

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19629>
2022-11-19 03:38:19 +00:00
David Heidelberg 1facb6fbe8 ci/freedreno: disable flaking Civilization V
See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7491

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19862>
2022-11-19 02:22:30 +00:00
Yonggang Luo e5f0d222b1 util: Rename PIPE_ALIGN_STACK to UTIL_ALIGN_STACK and moved into util/compiler.h
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 778402f3b0 llvmpipe: fixes error: ‘enum pipe_blendfactor’ declared in lp_test_blend.c
error  message:
In file included from ../../src/gallium/drivers/llvmpipe/lp_test_blend.c:44:
../../src/gallium/drivers/llvmpipe/lp_bld_blend.h:47:21: error: ‘enum pipe_blendfactor’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   47 |                enum pipe_blendfactor factor_src,

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 6832a9433d util: convert usage of uint to unsigned in u_format.h
Because uint comes from pipe/p_compiler.h, and that depends will be removed in future

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo b728bed567 util: use void * instead of byte * for util_copy_rect in u_format.h
As ubyte comes from p_compiler.h,  so do not use it,
and the code calles util_copy_rect may use args with type uint8_t*, ubyte* or unsigned char*,
so use the type void* that consistence with memcpy

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 2f42ffcd02 tgsi: fixes error: ‘enum pipe_shader_type’ declared in tgsi_info.h
error message:
../../src/gallium/auxiliary/tgsi/tgsi_info.h:92:30: error: ‘enum pipe_shader_type’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   92 | tgsi_get_processor_name(enum pipe_shader_type processor);

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 887e0fdace aco: fixes error: 'uint' was not declared in aco_instruction_selection.cpp
uint is from pipe/p_compiler.h

error message:
../../src/amd/compiler/aco_instruction_selection.cpp:11061:4: error: 'uint' was not declared in this scope; did you mean 'rint'?
11061 |    uint en_mask = 1;

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 72cf2b540c util: Remove the usage of enum pipe_error in u_hash_table.*
Use 0 instead of PIPE_OK in u_hash_table.c

Because pipe_error and PIPE_OK is comes from pipe/p_defines.h that doesn't belong
to src/util/

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Yonggang Luo 8eff2c2223 util: Remove redundant #include "util/u_inlines.h" in u_trace.c
util/u_inlines.h is comes from src/gallium/auxiliary/util/u_inlines.h,
so when possible, do not use it under src/util folder

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>
2022-11-19 01:37:46 +00:00
Caio Oliveira fbe40720e0 intel/compiler: Remove redundant argument from brw_nir_create_passthrough_tcs
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19831>
2022-11-19 00:35:56 +00:00