18ef9398de
agx: Remove nir_register support
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We don't use it anymore, now that we can handle SSA form. Gets rid of
the most gross hack in the compiler.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
1c6bd0357f
agx: Update RA comment
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
4498799822
agx: Remove identity moves
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
860832e41b
agx: Split up RA from post-RA lowering
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This allows us to validate results in the middle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
ea065537cb
agx: Lower phi nodes to parallel copies
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Now we have an SSA RA :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
a2a947031a
agx: Mark the logical ends of blocks
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We need to insert parallel copies at the logical end of blocks, before branches.
Add a pseudo instruction signaling that. Cribbed from ACO.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
3f1e926bf4
agx: Use a dynarray for predecessors
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This imposes a fixed ordering, allowing phi sources to be implicitly ordered.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
d06394095b
agx: Optimize p_split(kill) specially
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Let's make sure these are allocated optimally.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
e16ad8f443
agx: Lower p_split after RA
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Using existing regalloc infrastructure.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
4fc023ed42
agx: Use a transfer graph for parallel copies
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Lifted from ir3. Algorithm is the same; the data structures and interface are
lightly modified to decouple from ir3's IR.
Sequentializing parallel copies after RA is tricky. ir3's implementation works
well enough, so I use that one.
Original implementation by Connor Abbott.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 22:00:00 -04:00
ff660dd637
agx: Track write registers more accurately
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We may not write a full 32-bit vec4, don't be so pessimistic.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 21:58:29 -04:00
0c82b5c99c
agx: Note that RA proceeds in dominance-order
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This is an important invariant for SSA-based RA to work.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 21:58:29 -04:00
81477f3809
agx: Implement some shader-db stats
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Instructions, bytes, and registers -- this should hold us over until we
can reverse the underlying uarch and get proper cycle estimations.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268 >
2022-05-01 21:58:29 -04:00
96c98e0d25
agx: Define p_extract for type converts
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Useful for grabbing the high 32-bit word of a 64-bit value.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053 >
2021-07-24 17:25:40 -04:00
3c1f754a71
agx: Handle load_instance_id
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Preloaded into r6, as predicted.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053 >
2021-07-24 15:12:18 -04:00
465224379c
agx: Plug memory leak in register allocator
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Fixes: 85e18deb18https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053 >
2021-07-24 15:00:22 -04:00
7848100f27
agx: Use consistent ncomps
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Fixes register allocation failure in:
dEQP-GLES3.functional.ubo.single_basic_array.shared.row_major_mat4_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053 >
2021-07-24 14:55:16 -04:00
cce1a2fc19
agx: Dump register file when failing to allocate
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Usually shows a bug.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053 >
2021-07-24 14:54:34 -04:00
1d0008734c
agx: Ensure we don't overallocate registers
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751 >
2021-07-07 03:31:43 +00:00
85e18deb18
agx: Assign registers locally
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751 >
2021-07-07 03:31:43 +00:00
15b49a6795
agx: Count read registers as well
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11751 >
2021-07-07 03:31:43 +00:00
2e1ba82060
agx: Count write registers, not components
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718 >
2021-07-05 20:56:04 +00:00
ebd25e7ee7
agx: Pull out agx_write_components
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718 >
2021-07-05 20:56:04 +00:00
3d3e4928b2
agx: Add ld_vary_flat opcode
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718 >
2021-07-05 20:56:03 +00:00
1164c992cf
agx: Add ld_tile opcode
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Variant of st_tile.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10720 >
2021-05-09 23:29:45 -04:00
c215895eae
agx: Add a trivial register allocator
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582 >
2021-05-02 17:41:12 -04:00
Alyssa Rosenzweig
Alyssa Rosenzweig