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43 Commits

Author SHA1 Message Date
Caio Oliveira 3567d47f3e intel/genxml: Inline the BODY structs into the instructions 
Follows the convention used in other instructions.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657>
 2021-11-04 21:01:13 +00:00
Caio Oliveira 3fe2e862b5 intel/genxml: Add Mesh Shading structures 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13657>
 2021-11-04 21:01:13 +00:00
Kenneth Graunke 2f58a63b2f intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later. 
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP.  XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands.  iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
 2021-10-28 14:17:32 -07:00
Kenneth Graunke 9163500aa1 intel/genxml: Allow MI_FLUSH_DW on the blitter 
Pretty sure this is how you flush the blitter.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
 2021-10-28 14:17:32 -07:00
Kenneth Graunke 7b78b2fcac intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+ 
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
 2021-10-28 19:45:56 +00:00
Kenneth Graunke 956effb88a intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field 
This is redundant with the existing "MOCS" field.  We don't need both.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
 2021-10-28 19:45:55 +00:00
Sagar Ghuge 2b86cf2850 intel/genxml: Add new Primitive ID Not Required bit field to 3DSTATE_DS 
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>
 2021-10-26 18:22:14 +00:00
Anuj Phogat 1d224e7f14 genxml/gen125: Update 3DSTATE_TE fields 
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
 2021-10-13 22:36:54 +00:00
Jordan Justen 9a7e54b87f intel/genxml: Update genxml to support tessellation/geometry distribution 
Rework:
- Fix 3DSTATE_VFG opcode (Lionel)
- Fix distribution mode values (Sagar)
- Update 3DSTATE_VFG fields (Anuj)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>
 2021-10-13 22:36:54 +00:00
Sagar Ghuge e5265c023d intel/genxml: Add new bit fields Render Compression Format 
Add RenderCompressionFormat bit field in 3DSTATE_DEPTH/STENCIL_BUFFER
and RENDER_SURFACE_STATE packet to use compression format encoding for
Unified Losless Compression.

v2: (Nanley)
- Drop default value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>
 2021-10-08 18:56:14 +00:00
Jason Ekstrand 1f7e11a190 genxml: Drop bit 27 from RENDER_SURFACE_STATE::Surface Format 
Bit 27 is the "ASTC Format" bit in the PRMs but we just extended the
Surface Format field by one bit and made sure all the ASTC formats have
that bit set.  Since Gfx12.5 doesn't support ASTC, we can drop that bit
from the field and this will cause GenXML packing functions to assert if
it's ever set.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
 2021-10-06 15:04:33 +00:00
Jason Ekstrand 3e13c4ccf2 anv,iris,genxml: Use NumberOfBarriers on XeHP 
Ref: bspec 55400
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
 2021-09-30 17:41:33 +00:00
Nanley Chery af40104e7d intel: Add underscores to HALIGN and VALIGN enums 
The HALIGN enums for XeHP already have underscores. Make the other
HALIGN and VALIGN enums conform.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 3d1f6342c0 intel: Update surface states for XeHP alignments 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery 79ad9cda48 intel: Support Tile4/64 in surface states 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Nanley Chery dd9ae2dc7b intel: Support Tile4/64 in depth/stencil state 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12132>
 2021-08-25 22:39:30 +00:00
Marcin Ślusarz 4f4f3b1072 genxml: add INSTDONE_GEOM register for Gfx12.5 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12392>
 2021-08-17 08:05:45 +00:00
Lionel Landwerlin bee7bff48e genxml: add more INSTDONE registers for Gfx12.5 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12392>
 2021-08-17 08:05:45 +00:00
Sagar Ghuge 5ed5d08141 genxml/gen125: Update debug register fields according to HW 
Updating fields helps to decode the error state correctly.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12133>
 2021-08-02 16:45:31 +00:00
Iván Briano 004fcfe698 anv: fix some multisample lines_wide CTS tests 
We can use a better algorithm from ICL and onward by setting a chicken
bit, but prior to that we need to resort to disabling rectangular lines.
Since we don't support strictLines anyway, this shouldn't be a major
issue.

Closes #2833
Fixes dEQP-VK.rasterization.interpolation_multisample_*_bit.*lines_wide

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11672>
 2021-07-15 17:07:35 +00:00
Jason Ekstrand 63e80d441a intel/genxml: Remove old scratch fields on GFX version 12.5 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Jason Ekstrand 8ca0513eca intel/genxml: Add new ScratchSpaceBuffer fields on GFX version 12.5 
Rework:
 * Jordan: Fix MEMZONE_BINDER_START detection
 * Jordan: Bump the IRIS_BINDLESS_SIZE to 8M

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Jason Ekstrand 443627fcc0 intel/genxml: Add SURFTYPE_SCRATCH on GFX version 12.5 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11582>
 2021-06-25 00:18:29 +00:00
Jordan Justen eb98171252 intel/gen125.xml: Drop GPGPU_WALKER 
Ref: f4902bb189 ("intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11489>
 2021-06-21 19:40:14 +00:00
Dave Airlie c6f34e9fda intel/genxml: rewrite the prefilterop xml to be more consistent. 
This uses a prefix at Ken's suggestion and aligns it across gens

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
 2021-05-05 02:56:20 +00:00
Lionel Landwerlin b1622af394 intel/genxml: Add coarse pixel shading instructions 
v2: Add Gen12.5

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7455>
 2021-05-02 20:20:06 +00:00
Felix DeGrood ed94528711 intel: add L3 Bypass Disable to gen xml 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10217>
 2021-04-15 04:54:40 +00:00
Anuj Phogat e7e55af4d6 intel: Rename GENx keyword to GFXx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "GEN[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/GEN\([[:digit:]]\+\)/GFX\1/g"

Exclude the changes to modifiers:
grep -E "I915_.*GFX" -rIl $SEARCH_PATH | xargs sed -ie "s/\(I915_.*\)GFX/\1GEN/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Anuj Phogat 1d296484b4 intel: Rename Genx keyword to Gfxx 
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
 2021-04-02 18:33:07 +00:00
Jason Ekstrand 79d9c914ae intel/genxml: Make BindingTablePoolEnable a bool 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:46:50 -05:00
Jason Ekstrand 65077cdf57 intel/genxml: Binding table pointers are 15 bits on GFX version 12.5+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9729>
 2021-03-20 12:33:16 -05:00
Jordan Justen 16d453da7f genxml/gen12: 3D_MODE bits 31:16 are no longer must-be-one 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
 2021-03-19 09:07:37 +00:00
Jason Ekstrand 6721925220 genxml: Clean up MI_SET_PREDICATE 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:47:19 -06:00
Jason Ekstrand c7c524337a intel/mi_builder: Add load/store_offest on GFX 12.5+ 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:47:18 -06:00
Sagar Ghuge 04d0d4e849 intel/mi_builder: Added support for command streamer shift operations 
Add logical shift left and right operations support to mi_builder.

v1:
- Add GEN_GEN > 12 check (Jordan Justen)
- Add gen_mi_has_shift function (Jordan Justen)
- Fix commit title (Jordan Justen)

v2 (Jason Ekstrand):
- Add _imm versions of all of them
- Better handle corner-cases in _imm helpers
- Handle the power-of-two limitation for _imm versions
- Add tests

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9445>
 2021-03-08 10:45:42 -06:00
Jordan Justen 36dd7c44f6 intel: Use GEN_VERSIONx10 in more places 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
 2021-03-01 22:00:08 -08:00
Francisco Jerez ab076e19ed intel/genxml: Define 3DSTATE_SUBSLICE_HASH_TABLE command for Gen12 and Gen12.5. 
This command allows programming custom pixel hashing tables
controlling the balancing of load across pixel pipes.  Rather
confusingly 3DSTATE_SLICE_TABLE_STATE_POINTERS was serving the same
purpose on Gen11: A pixel is mapped to the pixel pipe with index
specified by the entry in the table corresponding to the LSBs of the
pixel coordinates [Yes you read right the entries are neither subslice
nor slice indices!].  Either a 2-way or a 3-way table can be
programmed based on whether the platform has two or three pixel pipes
per slice.  In addition the 16x8 tables defined below can hold two
separate 8x8 tables when in DUAL_TABLE mode (which AFAIA is only
useful for platforms with multiple asymmetric slices -- I.e. no
production platforms as of today to my knowledge).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
 2021-02-23 21:14:57 -08:00
Francisco Jerez a2a17bf25e intel/genxml: Fix pixel hashing 3DSTATE_3D_MODE field definitions for Gen12 and Gen12.5. 
The former "Subslice Hashing Mode" field is no longer used by the
hardware, Gen12 parts always do 16x16 subslice pixel hashing -- Remove
it since it's no longer useful.  In addition add a couple of bits that
will be useful in order to make some adjustments to the default pixel
pipe hashing behavior.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8749>
 2021-02-23 21:14:42 -08:00
Lionel Landwerlin e484478727 genxml: Add PIPE_CONTROL protected memory bits 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9127>
 2021-02-18 11:20:55 +02:00
Lionel Landwerlin 1b43528ade genxml: add MI_SET_APPID on Gen12+ 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9127>
 2021-02-18 11:20:51 +02:00
Jason Ekstrand f4902bb189 intel/genxml,anv,iris: Drop the legacy compute path from gen125.xml 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:28 -08:00
Jordan Justen cdc9e22a3a intel/genxml/gen125: Add CFE_STATE and COMPUTE_WALKER 
Reworks:
 * Jason: Captalize COMPUTE_WALKER::BTD mode
 * Jason: Make COMPUTE_WALKER::InlineData an array
 * Jason: Remove stale fields, uint=>bool, add missing enum values.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8342>
 2021-01-13 13:10:27 -08:00
Jordan Justen 569afd37f1 intel/genxml: Copy gen12.xml to gen125.xml 
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7757>
 2020-12-01 19:06:22 +00:00