Commit Graph

60903 Commits

Author SHA1 Message Date
José Fonseca ecaa81bd96 c11: Import threads.h emulation library.
Implementation is based of https://gist.github.com/2223710 with the
following modifications:
- inline implementatation
- retain XP compatability
- add temporary hack for static mutex initializers (as they are not part
  of the stack but still widely used internally)
- make TIME_UTC a conditional macro (some system headers already define
  it, so this prevents conflict)
- respect HAVE_PTHREAD macro

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Chad Versace <chad.versace@linux.intel.com>
2014-01-23 12:55:55 +00:00
José Fonseca 349f0a94ae os: Remove pipe_static_condvar.
Never used.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-23 12:55:55 +00:00
Timothy Arceri 815e064fb6 docs: Mark ARB_arrays_of_arrays as started
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:37:37 +11:00
Timothy Arceri b0c64d3cc6 glsl: remove remaining is_array variables
Previously the reason we needed is_array was because we used array_size == NULL to
 represent both non-arrays and unsized arrays.  Now that we use a non-NULL
array_specifier to represent an unsized array, is_array is redundant.

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:37:37 +11:00
Timothy Arceri 61a5846099 glsl: create type name for arrays of arrays
We need to insert outermost dimensions in the correct spot otherwise
 the dimension order will be backwards

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:37:36 +11:00
Timothy Arceri 3d492f19f6 glsl: Allow arrays of arrays as input to vertex shader
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:37:36 +11:00
Timothy Arceri 3dc932d450 glsl: only call mark_max_array if we are assigning an
array

This change does not help fix or prevent any bugs
it just seems reasonable to do

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:37:36 +11:00
Timothy Arceri bfb48750f0 glsl: Add ARB_arrays_of_arrays support to yacc definition and ast
Adds array specifier object to hold array information

Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:31:10 +11:00
Timothy Arceri 72288e0c7b mesa: Add ARB_arrays_of_arrays
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 23:15:29 +11:00
Topi Pohjolainen bda88f121b i965/blorp: switch eu-emitter to use FS IR and fs_generator
No regressions on IVB (piglit quick + unit tests).

v2 (Paul):
  - no need to patch the unit tests anymore. Original logic
    was altered and unit tests updated to match the
    fs-generator
  - lrp emission moves from the blorp compiler core into the
    emitter here (previously there was a separate refactoring
    patch which is not really needed anymore as the lrp logic
    got refactored when the original lrp logic got fixed).
  - pass 'BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX' to the
    generator in fs_inst::target instead of hardcoding it

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:47:12 +02:00
Topi Pohjolainen 8f3e5363ad i965/fs: add support for BRW_OPCODE_AVG in fs_generator
Needed for compiling blorp blit programs.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:47:12 +02:00
Topi Pohjolainen 9927d7ae68 i965/fs: introduce blorp specific rt-write for fs_generator
The compiler for blorp programs likes to emit instructions for
the message construction itself meaning that the generator needs
to skip any such when blorp programs are translated for the hw.
In addition, the binding table control is special for blorp
programs and the generator does not need to update the binding
tables associated with the compiler bookkeeping (this in fact
gets thrown away as the blorp compiler sets the program data
in its own way).

v2 (Paul): do not hardcode the binding table index but use
           fs_inst::target instead.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:46:57 +02:00
Topi Pohjolainen 85fc724df5 i965/fs: allow unit tests to dump the final patched assembly
Unit tests comparing generated blorp programs to known good need
to have the dump in designated file instead of in default
standard output. The comparison also expects the jump counters
of if-else-instructions to be correctly set and hence the dump
needs to be taken _after_ 'patch_IF_ELSE()' is run (the default
dump of the fs_generator does this before).

v2 (Paul): dropped the redundant 'dump_enabled' argument

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:57 +02:00
Topi Pohjolainen 757b4cf011 i965/blorp: wrap brw_IF/ELSE/ENDIF() into eu-emitter
v2 (Paul): renamed emit_if() to emit_cmp_if()

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:53 +02:00
Topi Pohjolainen 8c0030678a i965/blorp: wrap RNDD (/brw_RNDD(&func, /emit_rndd(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:51 +02:00
Topi Pohjolainen 44524cb42f i965/blorp: wrap FRC (/brw_FRC(&func, /emit_frc(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:49 +02:00
Topi Pohjolainen f9d875926e i965/blorp: wrap MUL (/brw_MUL(&func, /emit_mul(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:47 +02:00
Topi Pohjolainen bbab8068d2 i965/blorp: wrap OR (/brw_OR(&func, /emit_or(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:44 +02:00
Topi Pohjolainen de6ea2fe25 i965/blorp: wrap SHL (/brw_SHL(&func, /emit_shl(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:42 +02:00
Topi Pohjolainen d256a5f843 i965/blorp: wrap SHR (/brw_SHR(&func, /emit_shr(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:39 +02:00
Topi Pohjolainen 0df1f5ce4e i965/blorp: wrap ADD (/brw_ADD(&func, /emit_add(/)
In addition, the special case requiring explicit execution size
control is wrapped manually.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:37 +02:00
Topi Pohjolainen c777e72bd8 i965/blorp: wrap AND (/brw_AND(&func, /emit_and(/)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:34 +02:00
Topi Pohjolainen 8b5fd98043 i965/blorp: wrap MOV (/brw_MOV(&func, /emit_mov(/)
In addition, the two special cases requiring explicit execution
size control are wrapped manually.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:30 +02:00
Topi Pohjolainen 250494f742 i965/blorp: wrap emission of if-equal-assignment
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:28 +02:00
Topi Pohjolainen 9e9617f797 i965/blorp: wrap emission of conditional assignment
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:25 +02:00
Topi Pohjolainen 8c42ade7a4 i965/blorp: move emission of sample combining into eu-emitter
v2 (Paul): pass the combining opcode as an argument to emit_combine().
           This keeps manual_blend_average() selfcontained
           documentation wise.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:16 +02:00
Topi Pohjolainen ecf795615c i965/blorp: move emission of rt-write into eu-emitter
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:13 +02:00
Topi Pohjolainen aac6bace9f i965/blorp: move emission of texture lookup into eu-emitter
Resolving of the hardware message type is moved into the
emitter also in preparation for switching to use fs_generator.
The generator wants to translate the high level op-code into
the message type and hence the emitter needs to know the
original op-code.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:10 +02:00
Topi Pohjolainen 41d397f22b i965/fs: introduce non-compressed equivalent of tex_cms
v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:45:04 +02:00
Topi Pohjolainen ce527a6722 i965: rename tex_ms to tex_cms
Prepares for the introduction of non-compressed multi-sampled
lookup used in the blorp programs.

v2: now also taking into account gen8

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:44:58 +02:00
Topi Pohjolainen 3c44e43357 i965/blorp: move emission of pixel kill into eu-emitter
The combination of four separate comparison operations and
and the masked "and" require special treatment when moving
to FS LIR.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:44:52 +02:00
Topi Pohjolainen f031487dcb i965/blorp: introduce separate eu-emitter for blit compiler
Prepares for presenting blorp blit programs using FS IR that
allows EU-assembly generation using i965 glsl-compiler
backend (fs_generator).

v2: rebased on top of endif-jump counter fix (moving the
    added brw_set_uip_jip() into the emitter)

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-23 08:44:44 +02:00
Kenneth Graunke d8c7740dda i965: Support 32 texture image units on Haswell+.
The Intel closed source OpenGL driver recently began supporting 32
texture image units on Haswell.  This makes the open source driver
support 32 as well.

Earlier generations don't have the message header field required to
support more than 16 sampler states, so we continue to advertise 16
there.

On Haswell, this causes us to advertise:
- GL_MAX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
instead of the old values of 16, 16, and 48.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:58 -08:00
Kenneth Graunke 5a51a26804 i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.
BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to
support the new larger value.  On older platforms, we don't want to
allocate the extra space - it would just be a waste.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:56 -08:00
Kenneth Graunke 50ce6f682d mesa: Bump MAX_TEXTURE_IMAGE_UNITS to 32.
This allows drivers to optionally support more than 16 texture units.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:55 -08:00
Kenneth Graunke 15fc919491 i965/vec4: Support arbitrarily large sampler state indices on Haswell+.
Like the scalar backend, we add an offset to the "Sampler State Pointer"
field to select a group of 16 samplers, then use the "Sampler Index"
field to select within that group.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:53 -08:00
Kenneth Graunke d58e03fe4f i965/vec4: Refactor sampler message setup.
The next patch adds an additional case where the message header is
necessary.  So we want to do the g0 copy if inst->header_present is set,
rather than inst->texture_offset.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:51 -08:00
Kenneth Graunke e0a5602911 i965/vec4: Don't set header_present if texel offsets are all 0.
In theory, a shader might use textureOffset() but set all the texel
offsets to zero.  In that case, we don't actually need to set up the
message header - zero is the implicit default.

By moving the texture_offset setup before the header_present setup, we
can easily only set header_present when there are non-zero texel offset
values.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:49 -08:00
Kenneth Graunke 6943ac0bd9 i965/fs: Support arbitrarily large sampler state indices on Haswell+.
The message descriptor's "Sampler Index" field is only 4 bits (on all
generations of hardware), so it can only represent indices 0 through 15.

Haswell introduced a new field in the message header - "Sampler State
Pointer".  Normally, this is copied straight from g0, but we can also
add a byte offset (as long as it's a multiple of 32).

This patch uses a "Sampler State Pointer" offset to select a group of
16 sampler states, and then uses the "Sampler Index" field to select
the state within that group.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:48 -08:00
Kenneth Graunke d7450e52e6 i965/fs: Plumb sampler index into emit_texture_gen7.
We'll need this in the next patch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:46 -08:00
Kenneth Graunke ebfe43d5ad i965/fs: Refactor sampler message header to duplicate less code.
Previously, the code to copy g0 to the message header existed in two
places - one for the texture offset case, and one for any other case.

By treating texture_offset as a special case of header_present, we can
remove this duplication and shorten the code.  Future patches which add
new header fields also won't have to add additional duplication.

This also clarifies a confusing construct.  The old code contained:

   } else if (inst->header_present) {
      if (brw->gen >= 7) {
         ...explicit copy from g0 to the message header...
      } else {
         /* Set up an implied move from g0 to the MRF. */
      }
   }

This looks like it might set up an implied move on Sandybridge, which
doesn't support those.  However, Sandybridge only uses a message header
for texture offsets, so it would never hit this code path.  The new code
avoids this implicit knowledge by only setting up an implied move on
Gen4-5.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:42 -08:00
Kenneth Graunke 87e7326735 i965: Use get_element_ud to shorten texture header access.
This is shorter, easier to read, and further from the 80 column limit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-22 17:18:18 -08:00
Marek Olšák d40532f260 gallium/util: util_format_srgb should not return FORMAT_NONE for sRGB formats
This fixes a serious regression introduced
in 4e549ddb50.

Cc: 9.2 10.0 <mesa-stable@lists.freedesktop.org>

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-23 01:47:14 +01:00
Marek Olšák d382e90614 gallium: remove PIPE_CAP_SCALED_RESOLVE
If any driver doesn't support this, it can use a blit after resolving
the samples.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-01-23 01:47:14 +01:00
Marek Olšák a8930adbf8 radeonsi: use hardware scissors correctly
Use the WINDOW and VPORT scissors for the framebuffer and scissor test,
respectively. The other two scissors are disabled (they cover the max fb size).

We actually have 16 VPORT scissors, which will map well to ARB_viewport_array.

Also, we don't need to write SC_WINDOW_OFFSET with this commit, because it's
disabled everywhere.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-01-23 01:47:14 +01:00
Marek Olšák 69c29cb147 radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flush
For consistency only, This is unused by radeonsi currently.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-01-23 01:47:14 +01:00
Marek Olšák 5dfb10b2f5 r600g,radeonsi: if discarding whole buffer range, discard whole resource instead
Also set the unsynchronized flag if the whole resource was discarded
to avoid doing buffer-busy checks again.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-01-23 01:47:14 +01:00
Marek Olšák ee0dc659c8 gallium/u_upload_mgr: don't expose u_upload_flush
It's unused and shouldn't be used at all in my opinion.

If some driver doesn't support the unsynchronized flag, u_upload_mgr should
avoid the synchronization by other means, e.g. by using the DONTBLOCK flag.
2014-01-23 01:47:14 +01:00
Marek Olšák 0c20bff4b6 gallium/hud: just unmap the upload vertex buffer instead of recreating it 2014-01-23 01:47:14 +01:00
Marek Olšák 2b033f3aab gallium/vl: use u_upload_mgr to upload vertices for vl_compositor
This is the recommended way for streaming vertices. Always use this if you
need to upload vertices every frame.

Reviewed-by: Christian König <christian.koenig@amd.com>
2014-01-23 01:47:14 +01:00