Commit Graph

58 Commits

Author SHA1 Message Date
Ian Romanick 3fa16b3025 intel/isl: Add mappings for PIPE_FORMAT_R8G8_R8B8_UNORM and PIPE_FORMAT_G8R8_B8R8_UNORM
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
2021-05-21 01:40:22 +00:00
Marcin Ślusarz 7e6a7dba1e intel/isl: replace format_gen by verx10
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
2021-05-17 09:46:45 +00:00
Jordan Justen 89f3312625 intel/isl: Add Wa_22011186057 to disable CCS on ADL GT2 A0
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
2021-05-14 06:10:47 +00:00
Lionel Landwerlin df0580312a isl: document format fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
2021-05-05 12:20:09 +00:00
Jason Ekstrand b80720acb1 intel/isl: Fix isl_color_value_unpack to match the prototype
The prototype uses a pointer and the actual function definition had an
array.  For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.

Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
2021-04-30 17:01:05 +00:00
Anuj Phogat 61e8636557 intel: Rename gen_device prefix to intel_device
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
2021-04-20 20:06:33 +00:00
Anuj Phogat cd39d3b1ad intel: Rename gen_device prefix in filenames
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "gen_device" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen_device/intel_device}"' \;
grep -E "gen_device_info*\.[cph]" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device_info\(.*\.[cph]\)/intel_device_info\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
2021-04-20 20:06:33 +00:00
Anuj Phogat 1d296484b4 intel: Rename Genx keyword to Gfxx
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat b75f095bc7 intel: Rename genx keyword to gfxx in source files
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat abe9a71a09 intel: Rename gen field in gen_device_info struct to ver
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Nanley Chery 5e27e04322 intel/isl: Drop redundant unpack of unorm channels
Fixes: 09ced65420 ("intel/isl: Add format conversion code")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7168>
2020-10-16 18:35:57 +00:00
Sagar Ghuge 3547e19bbd intel/isl: Switch to R8_UNORM format for compatiblity
Gen12 added CCS_E support for A8_UNORM. Intercept A8_UNORM format and
switch to R8_UNORM, as both share the same aux map format encoding so
they are compatible.

Fixes Piglit's ext_framebuffer_multisample-formats all_samples, which
was hitting an assert about A8_UNORM and R8_UINT not being CCS_E
compatible formats.

v2: Add gen check (Kenneth Graunke)

v3: Intercept A8_UNORM and set format to R8_UNORM (Jason Ekstrand)

v4:
- Remove gen check and move block little bit down (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
2020-02-13 18:44:50 +00:00
Eric Anholt 5bea0cf779 intel/isl: Move iris's pipe-to-isl format function to isl.
This will get reused in the shader compiler once we switch it over to pipe
formats instead of GL enums.  We can't easily deduplicate i965's
mesa-to-isl mapping because of cases like A32_FLOAT that are mapped
differently.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
2020-02-05 10:31:09 -08:00
Jason Ekstrand 4d03e53127 intel/isl: Allow CCS_E on more formats
Now that BLORP supports copies on everything except R11G11B10_FLOAT,
we should be able to support CCS_E those formats.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
2020-01-25 17:48:54 +00:00
Nanley Chery 6670e07a6e intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 10:47:05 -07:00
Nanley Chery e655eed531 intel: Enable CCS_E for some formats on Gen12
In ISL:
   Update the format table to add CCS_E support for some 8BPP formats,
   some 16BPP formats, and R10G10B10A2_UNORM_SRGB.

   In the helper for determining CCS_E support, we return false for some
   16BPP formats because they aren't properly handled in blorp_copy().

In BLORP:
   Allow the new and non-problematic formats for CCS_E-enabled copies.

v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
2019-10-28 10:47:05 -07:00
Nanley Chery a94cb6503f isl: Disable CCS_D on Gen12+
Clear-only compression no longer exists on TGL.

v2. Add BSpec reference. (Sagar)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 10:47:04 -07:00
Jordan Justen d83fe059c2 intel/isl: Add R10G10B10_FLOAT_A2_UNORM format
Reworks:
 * Fill out the format's entry in the ISL format table. (Nanley)
 * Support CCS_E-enabled BLORP copies with the format. (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-17 21:21:56 -07:00
Jason Ekstrand 7c1b39cf18 isl/formats: R8G8B8_UNORM_SRGB isn't supported on HSW
On Haswell, the format works but it doesn't properly do an sRGB decode.
It appears to act identically to R8G8B8_UNORM.  Only Vulkan uses this
format so this only affects Vulkan on HSW.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-07-29 11:34:18 -05:00
Rafael Antognolli d97eddff25 intel/isl: Add isl_format_has_color_component() function.
v2: Get luminance bits from luminance component (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Jason Ekstrand 3b54dd87f7 intel/isl: Add bounds-checking assertions for the format_info table
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in.  We also
check against the array size of the table because some valid formats
such as CCS formats will may be past the end of the table.  This fixes
some potential out-of-bounds array access even in valid cases.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-06-07 11:23:34 -07:00
Jason Ekstrand 399962e7c6 intel/isl: Several UNORM formats support typed writes on gen11+
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2018-05-10 14:12:55 -07:00
Jason Ekstrand 561348caa1 intel/isl: Allow CCS_E on 1010102 formats
On CNL and above, CCS_E supports 1010102 formats and R11G11B10F.  We had
shut them off during early enabling because blorp_copy couldn't handle
them.  Now it can handle 1010102 formats so we can turn them back on.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09 11:16:33 -07:00
Jason Ekstrand 09ced65420 intel/isl: Add format conversion code
This adds helpers to ISL to convert an isl_color_value to and from
binary data encoded with a given isl_format.  The conversion is done
using ISL's built-in format introspection so it's fairly slow as format
conversions go but it should be fine for a single pixel value.  In
particular, we can use this to convert clear colors.

As a side-effect, we now rely on the sRGB helpers in libmesautil so we
need to tweak the build system a bit.  All prior uses of src/util in ISL
were header-only.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09 11:16:33 -07:00
Jason Ekstrand 08cd834996 intel/isl: Add some helpers for working with RGBX formats
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-05-09 11:16:33 -07:00
Jordan Justen 272bef0601 intel: Split gen_device_info out into libintel_dev
Split out the device info so isl doesn't depend on intel/common. Now
it will depend on the new intel/dev device info lib.

This will allow the decoder in intel/common to use isl, allowing us to
apply Ken's patch that removes the genxml duplication of surface
formats.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-03-05 09:47:37 -08:00
Nanley Chery c7baaafe54 intel/isl: Disable some gen10 CCS_E formats for now
CannonLake additionally supports R11G11B10_FLOAT and four 10-10-10-2
formats with CCS_E. None of these formats fit within the current
blorp_copy framework so disable them until support is added.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-31 14:26:23 -07:00
Matt Turner 9fdbc273ef intel/isl: Remove 'inline' keywords
Unless you have data, the compiler knows better than you whether a
function should be inlined.

Unlike all other cases in this series, the removal of the inline keyword
from isl_format_has_channel_type actually changes the resulting binary
with gcc-6.3.0:

   text	   data	    bss	    dec	    hex	filename
7831116	 346384	 420648	8598148	 833284	i965_dri.so before
7830716	 346384	 420648	8597748	 8330f4	i965_dri.so after

I think this is likely an improvement. No difference in the resulting
binary with clang-4.0.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Topi Pohjolainen abb84e3f2d intel/isl/gen7: Allow msaa with 128-bit formats
These formats are already allowed by the i965 GL driver, and the
feature seems to work just fine.

There are tests for multisampled rendering in piglit:
tests/spec/ext_framebuffer_multisample which can be patched to
try GL_RGBA16F/32F/16I/16UI/32I/32UI in addition to GL_RGBA/8I.
IvyBridge passed all tests with all sample numbers and even
with 128-bit formats.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22 00:14:16 +03:00
Lionel Landwerlin 030abc6109 intel: compiler/i965: fix is_broxton checks
In 5f2fe9302c is_geminilake was introduced for the differenciate
broxton from geminilake. Unfortunately I failed as verifying that
is_broxton is throughout the code base to mean Gen9lp.

Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-20 23:26:42 +01:00
Anuj Phogat 9acc93feeb i965/cnl: Enable CCS_E and RT support for few formats
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Anuj Phogat 61f171292e i965/cnl: Reformat surface_format_info table to accomodate gen10+
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-09 16:02:59 -07:00
Nanley Chery 52a6fd9871 intel/isl: Add ASTC HDR to format lists and helpers
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-05-22 11:13:53 -07:00
Nanley Chery 50134cede1 isl/format: Update the R16G16B16X16_FLOAT entry
The section of the PRM mentioned in the code comment above this table
says that this format supports the render target write message. Internal
documentation says that this format also supports alpha blending. As a
side effect, this allows CCS_D buffers to be created for images with
this format.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-04-24 13:30:50 -07:00
Jason Ekstrand f8dfe9b826 intel/isl: Add format metadata for typed reads/writes
This adds two columns to the format table as well as two helpers for
determining whether or not a given format is supported for typed reads
and writes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-14 07:50:13 -08:00
Jason Ekstrand 37a6f48ceb intel/isl: Add a better comment for format_supports_ccs_e
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 7e6a9d9c4b intel/isl: Add a formats_are_ccs_e_compatible helper
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 6142e3c07c intel/isl: Add a format_supports_ccs_d helper
Nothing uses this yet but it serves as a nice bit of documentation
that's relatively easy to find.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand ab06fc6684 intel/isl: Rename supports_lossless_compression to supports_ccs_e
The term "lossless compression" could potentially mean multisample
color compression, single-sample color compression or HiZ because they
are all lossless.  The term CCS_E, however, has a very precise meaning;
in ISL and is only used to refer to single-sample color compression.
It's also much shorter which is nice.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2017-02-02 13:33:43 -08:00
Jason Ekstrand 4871930451 isl/formats: Only advertise sampling for A4B4G4R4 on Broadwell
This causes hangs on Broadwell if you try to render to it.  I have no
idea how we managed to not hit this earlier.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-01-31 18:49:44 -08:00
Samuel Iglesias Gonsálvez 3551a2d3ad isl: fix VA64 support for double and dvecN vertex attributes
We use *64*_PASSTHRU formats to upload vertex attributes of 64 bits
to avoid conversions. From the BDW PRM, Volume 2d, page 586
(VERTEX_ELEMENT_STATE):

     "When SourceElementFormat is set to one of the *64*_PASSTHRU
     formats, 64-bit components are stored in the URB without any
     conversion. In this case, vertex elements must be written as 128
     or 256 bits, with VFCOMP_STORE_0 being used to pad the output
     as required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
     component into the URB, Component 1 must be specified as
     VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE)
     in order to output a 128-bit vertex element, or Components 1-3 must
     be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
     element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
     to be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
     element."

v2,v3 (Jason):
- Don't delete unused formats.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-09 09:10:13 +01:00
Jason Ekstrand 4e7958fb13 isl: Mark A4B4G4R4_UNORM as supported on gen8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
2017-01-06 16:44:15 -08:00
Nanley Chery 59385da39d isl/format: Correct ASTC entries of format info table
With the isl_format_supports* helpers, we can now conveniently
report support for this format on Cherry View.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-10-24 15:51:57 -07:00
Jason Ekstrand b1311a48e0 intel/isl: Allow multisampling with ISL_FORMAT_HiZ
HiZ buffers can be multisampled and, on Broadwell and earlier, simply using
interleaved multisampling with a compression block size of 8x4 samples
yields the correct HiZ surface size calculations.  Unfortunately,
choose_msaa_layout was rejecting multisampled HiZ buffers because of format
checks.  Now that we have a simple helper for determining if a format
supports multisampling, that's an easy enough issue to fix.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-10-03 14:53:01 -07:00
Jason Ekstrand 5637f3f120 intel/isl: Add a format_supports_multisampling helper
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-10-03 14:53:01 -07:00
Jason Ekstrand 527f371999 intel: s/brw_device_info/gen_device_info/
Generated by:

sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp
sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-03 08:23:06 -07:00
Jason Ekstrand 55364ab5b7 intel: Add a new "common" library for more code sharing
The first thing to go in this new library is brw_device_info.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-09-03 08:23:06 -07:00
Jason Ekstrand 70bc891c42 isl/formats: Integer formats are not filterable
In ca2a8e5628, we updated the format table to add more formats (most of
which are new on SKL) but accidentally marked some integer formats as
filterable.  You can't filter an integer format.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 16:51:34 -07:00
Jason Ekstrand ca2a8e5628 isl/formats: Update the table with more samplable formats
There were a lot of formats where support was added on Haswell or later but
we never updated the format table.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 11:45:24 -07:00
Jason Ekstrand aba9e25b70 isl/formats: Report ETC as being samplable on Bay Trail
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2016-08-23 11:45:24 -07:00