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agx: Add 32-bit bitwise shifts 

Only ishr has an actual native instruction, the others are special cases
of the bitfield insertion/extraction ops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
This commit is contained in:
Alyssa Rosenzweig 2021-04-17 09:58:20 -04:00 committed by Alyssa Rosenzweig
parent 17bb5a067a
commit e50bae00f4
1 changed files with 4 additions and 0 deletions
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4
src/asahi/compiler/agx_compile.c
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@ -263,6 +263,10 @@ agx_emit_alu(agx_builder *b, nir_alu_instr *instr)
case nir_op_ineg: return agx_iadd_to(b, dst, agx_zero(), agx_neg(s0), 0);
case nir_op_imul: return agx_imad_to(b, dst, s0, s1, agx_zero(), 0);
case nir_op_ishl: return agx_bfi_to(b, dst, s0, agx_zero(), s1, 0);
case nir_op_ushr: return agx_bfeil_to(b, dst, agx_zero(), s0, s1, 0);
case nir_op_ishr: return agx_asr_to(b, dst, s0, s1);
case nir_op_iadd_sat:
{
agx_instr *I = agx_iadd_to(b, dst, s0, s1, 0);