mirror of https://gitlab.freedesktop.org/mesa/mesa
intel/brw: Replace FS_OPCODE_LINTERP with BRW_OPCODE_PLN
We no longer support the old LINE+MAC lowering, and we already lower this to MAD in NIR on Gfx11+, so the LINTERP virtual opcode always corresponds the PLN. The only catch is that LINTERP's operands are reversed from PLN, so we have to switch them. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28705>
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@ -495,7 +495,6 @@ enum opcode {
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*/
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FS_OPCODE_DDY_COARSE,
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FS_OPCODE_DDY_FINE,
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FS_OPCODE_LINTERP,
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FS_OPCODE_PIXEL_X,
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FS_OPCODE_PIXEL_Y,
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FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
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@ -510,7 +510,6 @@ fs_inst::can_do_cmod() const
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case BRW_OPCODE_SHR:
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case BRW_OPCODE_SUBB:
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case BRW_OPCODE_XOR:
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case FS_OPCODE_LINTERP:
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break;
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default:
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return false;
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@ -721,11 +720,8 @@ fs_inst::components_read(unsigned i) const
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return 0;
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switch (opcode) {
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case FS_OPCODE_LINTERP:
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if (i == 0)
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return 2;
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else
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return 1;
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case BRW_OPCODE_PLN:
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return i == 0 ? 1 : 2;
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case FS_OPCODE_PIXEL_X:
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case FS_OPCODE_PIXEL_Y:
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@ -920,8 +916,8 @@ fs_inst::size_read(int arg) const
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return mlen * REG_SIZE;
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break;
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case FS_OPCODE_LINTERP:
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if (arg == 1)
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case BRW_OPCODE_PLN:
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if (arg == 0)
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return 16;
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break;
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@ -2422,9 +2418,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
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case FS_OPCODE_DDY_FINE:
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return "ddy_fine";
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case FS_OPCODE_LINTERP:
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return "linterp";
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case FS_OPCODE_PIXEL_X:
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return "pixel_x";
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case FS_OPCODE_PIXEL_Y:
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@ -500,8 +500,6 @@ private:
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struct brw_reg payload,
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struct brw_reg payload2);
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void generate_barrier(fs_inst *inst, struct brw_reg src);
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bool generate_linterp(fs_inst *inst, struct brw_reg dst,
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struct brw_reg *src);
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void generate_ddx(const fs_inst *inst,
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struct brw_reg dst, struct brw_reg src);
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void generate_ddy(const fs_inst *inst,
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@ -75,7 +75,6 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
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case FS_OPCODE_FB_READ_LOGICAL:
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case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
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case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
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case FS_OPCODE_LINTERP:
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case SHADER_OPCODE_FIND_LIVE_CHANNEL:
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case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
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case SHADER_OPCODE_LOAD_LIVE_CHANNELS:
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@ -603,31 +603,6 @@ fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
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}
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}
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bool
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fs_generator::generate_linterp(fs_inst *inst,
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struct brw_reg dst, struct brw_reg *src)
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{
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/* PLN reads:
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* / in SIMD16 \
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* -----------------------------------
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* | src1+0 | src1+1 | src1+2 | src1+3 |
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* |-----------------------------------|
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* |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
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* -----------------------------------
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*/
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struct brw_reg delta_x = src[0];
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struct brw_reg interp = src[1];
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/* nir_lower_interpolation() will do the lowering to MAD instructions for
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* us on gfx11+
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*/
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assert(devinfo->ver < 11);
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assert(devinfo->has_pln);
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brw_PLN(p, dst, interp, delta_x);
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return false;
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}
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/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
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* looking like:
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*
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@ -1216,8 +1191,16 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
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assert(inst->opcode == SHADER_OPCODE_POW || inst->exec_size == 8);
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gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
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break;
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case FS_OPCODE_LINTERP:
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multiple_instructions_emitted = generate_linterp(inst, dst, src);
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case BRW_OPCODE_PLN:
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/* PLN reads:
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* / in SIMD16 \
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* -----------------------------------
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* | src1+0 | src1+1 | src1+2 | src1+3 |
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* |-----------------------------------|
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* |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
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* -----------------------------------
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*/
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brw_PLN(p, dst, src[0], src[1]);
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break;
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case FS_OPCODE_PIXEL_X:
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assert(src[0].type == BRW_REGISTER_TYPE_UW);
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@ -254,18 +254,18 @@ brw_fs_lower_barycentrics(fs_visitor &s)
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const fs_builder ubld = ibld.exec_all().group(8, 0);
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switch (inst->opcode) {
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case FS_OPCODE_LINTERP : {
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case BRW_OPCODE_PLN: {
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assert(inst->exec_size == 16);
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const fs_reg tmp = ibld.vgrf(inst->src[0].type, 2);
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const fs_reg tmp = ibld.vgrf(inst->src[1].type, 2);
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fs_reg srcs[4];
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for (unsigned i = 0; i < ARRAY_SIZE(srcs); i++)
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srcs[i] = horiz_offset(offset(inst->src[0], ibld, i % 2),
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srcs[i] = horiz_offset(offset(inst->src[1], ibld, i % 2),
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8 * (i / 2));
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ubld.LOAD_PAYLOAD(tmp, srcs, ARRAY_SIZE(srcs), ARRAY_SIZE(srcs));
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inst->src[0] = tmp;
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inst->src[1] = tmp;
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progress = true;
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break;
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}
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@ -306,7 +306,7 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
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/* Integer division is limited to SIMD8 on all generations. */
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return MIN2(8, inst->exec_size);
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case FS_OPCODE_LINTERP:
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case BRW_OPCODE_PLN:
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case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
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case FS_OPCODE_PACK_HALF_2x16_SPLIT:
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case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
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@ -4310,7 +4310,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
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interp.type = BRW_REGISTER_TYPE_F;
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dest.type = BRW_REGISTER_TYPE_F;
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bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp);
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bld.PLN(offset(dest, bld, i), interp, dst_xy);
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}
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break;
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}
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@ -439,7 +439,7 @@ namespace {
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return calculate_desc(info, EU_UNIT_NULL, 8, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0);
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case FS_OPCODE_LINTERP:
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case BRW_OPCODE_PLN:
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return calculate_desc(info, EU_UNIT_FPU, 0, 4, 0, 0, 4,
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0, 12, 8 /* XXX */, 16 /* XXX */, 0, 0);
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@ -423,7 +423,6 @@ fs_inst::can_do_saturate() const
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case BRW_OPCODE_SEL:
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case BRW_OPCODE_SHL:
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case BRW_OPCODE_SHR:
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case FS_OPCODE_LINTERP:
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case SHADER_OPCODE_COS:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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@ -455,7 +454,6 @@ bool
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fs_inst::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const
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{
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return writes_accumulator ||
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(opcode == FS_OPCODE_LINTERP && !devinfo->has_pln) ||
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(eot && intel_needs_workaround(devinfo, 14010017096));
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}
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