mirror of https://gitlab.freedesktop.org/mesa/mesa
intel/fs: printout a couple of more late compile steps
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28188>
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@ -2246,7 +2246,7 @@ brw_emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst)
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void
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void
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fs_visitor::dump_instructions_to_file(FILE *file) const
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fs_visitor::dump_instructions_to_file(FILE *file) const
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{
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{
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if (cfg) {
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if (cfg && grf_used == 0) {
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const register_pressure &rp = regpressure_analysis.require();
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const register_pressure &rp = regpressure_analysis.require();
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unsigned ip = 0, max_pressure = 0;
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unsigned ip = 0, max_pressure = 0;
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unsigned cf_count = 0;
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unsigned cf_count = 0;
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@ -2265,6 +2265,13 @@ fs_visitor::dump_instructions_to_file(FILE *file) const
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cf_count += 1;
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cf_count += 1;
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}
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}
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fprintf(file, "Maximum %3d registers live at once.\n", max_pressure);
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fprintf(file, "Maximum %3d registers live at once.\n", max_pressure);
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} else if (cfg && exec_list_is_empty(&instructions)) {
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unsigned ip = 0;
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foreach_block_and_inst(block, fs_inst, inst, cfg) {
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fprintf(file, "%4d: ", ip);
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dump_instruction(inst, file);
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ip++;
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}
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} else {
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} else {
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int ip = 0;
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int ip = 0;
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foreach_in_list(fs_inst, inst, &instructions) {
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foreach_in_list(fs_inst, inst, &instructions) {
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@ -2996,10 +3003,16 @@ fs_visitor::allocate_registers(bool allow_spilling)
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if (failed)
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if (failed)
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return;
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return;
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debug_optimizer(nir, "post_ra_alloc", 96, 0);
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brw_fs_opt_bank_conflicts(*this);
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brw_fs_opt_bank_conflicts(*this);
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debug_optimizer(nir, "bank_conflict", 96, 1);
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schedule_instructions_post_ra();
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schedule_instructions_post_ra();
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debug_optimizer(nir, "post_ra_alloc_scheduling", 96, 2);
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if (last_scratch > 0) {
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if (last_scratch > 0) {
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ASSERTED unsigned max_scratch_size = 2 * 1024 * 1024;
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ASSERTED unsigned max_scratch_size = 2 * 1024 * 1024;
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