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amd/common: move some format related helpers to ac_formats.c 

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29291>
This commit is contained in:
Samuel Pitoiset 2024-05-20 15:54:17 +02:00 committed by Marge Bot
parent 473559001f
commit c62f86587f
6 changed files with 127 additions and 120 deletions
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118
src/amd/common/ac_formats.c
View File

@ -193,6 +193,124 @@ ac_translate_tex_numformat(const struct util_format_description *desc,
return num_format;
}
unsigned
ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
#define HAS_SIZE(x, y, z, w) \
(desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
desc->channel[2].size == (z) && desc->channel[3].size == (w))
if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
return V_028C70_COLOR_10_11_11;
if (gfx_level >= GFX10_3 &&
format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
return V_028C70_COLOR_5_9_9_9;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return V_028C70_COLOR_INVALID;
/* hw cannot support mixed formats (except depth/stencil, since
* stencil is not written to). */
if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
return V_028C70_COLOR_INVALID;
int first_non_void = util_format_get_first_non_void_channel(format);
/* Reject SCALED formats because we don't implement them for CB. */
if (first_non_void >= 0 && first_non_void <= 3 &&
(desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED ||
desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_SIGNED) &&
!desc->channel[first_non_void].normalized &&
!desc->channel[first_non_void].pure_integer)
return V_028C70_COLOR_INVALID;
switch (desc->nr_channels) {
case 1:
switch (desc->channel[0].size) {
case 8:
return V_028C70_COLOR_8;
case 16:
return V_028C70_COLOR_16;
case 32:
return V_028C70_COLOR_32;
case 64:
return V_028C70_COLOR_32_32;
}
break;
case 2:
if (desc->channel[0].size == desc->channel[1].size) {
switch (desc->channel[0].size) {
case 8:
return V_028C70_COLOR_8_8;
case 16:
return V_028C70_COLOR_16_16;
case 32:
return V_028C70_COLOR_32_32;
}
} else if (HAS_SIZE(8, 24, 0, 0)) {
return V_028C70_COLOR_24_8;
} else if (HAS_SIZE(24, 8, 0, 0)) {
return V_028C70_COLOR_8_24;
}
break;
case 3:
if (HAS_SIZE(5, 6, 5, 0)) {
return V_028C70_COLOR_5_6_5;
} else if (HAS_SIZE(32, 8, 24, 0)) {
return V_028C70_COLOR_X24_8_32_FLOAT;
}
break;
case 4:
if (desc->channel[0].size == desc->channel[1].size &&
desc->channel[0].size == desc->channel[2].size &&
desc->channel[0].size == desc->channel[3].size) {
switch (desc->channel[0].size) {
case 4:
return V_028C70_COLOR_4_4_4_4;
case 8:
return V_028C70_COLOR_8_8_8_8;
case 16:
return V_028C70_COLOR_16_16_16_16;
case 32:
return V_028C70_COLOR_32_32_32_32;
}
} else if (HAS_SIZE(5, 5, 5, 1)) {
return V_028C70_COLOR_1_5_5_5;
} else if (HAS_SIZE(1, 5, 5, 5)) {
return V_028C70_COLOR_5_5_5_1;
} else if (HAS_SIZE(10, 10, 10, 2)) {
return V_028C70_COLOR_2_10_10_10;
} else if (HAS_SIZE(2, 10, 10, 10)) {
return V_028C70_COLOR_10_10_10_2;
}
break;
}
return V_028C70_COLOR_INVALID;
}
unsigned ac_get_cb_number_type(enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
int chan = util_format_get_first_non_void_channel(format);
if (chan == -1 || desc->channel[chan].type == UTIL_FORMAT_TYPE_FLOAT) {
return V_028C70_NUMBER_FLOAT;
} else {
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
return V_028C70_NUMBER_SRGB;
} else if (desc->channel[chan].type == UTIL_FORMAT_TYPE_SIGNED) {
return desc->channel[chan].pure_integer ? V_028C70_NUMBER_SINT : V_028C70_NUMBER_SNORM;
} else if (desc->channel[chan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
return desc->channel[chan].pure_integer ? V_028C70_NUMBER_UINT : V_028C70_NUMBER_UNORM;
} else {
return V_028C70_NUMBER_UNORM;
}
}
}
unsigned
ac_translate_colorswap(enum amd_gfx_level gfx_level, enum pipe_format format, bool do_endian_swap)
{

6
src/amd/common/ac_formats.h
View File

@ -28,6 +28,12 @@ uint32_t
ac_translate_tex_numformat(const struct util_format_description *desc,
int first_non_void);
unsigned
ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format);
unsigned
ac_get_cb_number_type(enum pipe_format format);
unsigned
ac_translate_colorswap(enum amd_gfx_level gfx_level,
enum pipe_format format,

117
src/amd/common/ac_surface.c
View File

@ -4303,120 +4303,3 @@ nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *
htile_pitch, htile_slice_size,
x, y, z, pipe_xor, NULL);
}
unsigned ac_get_cb_number_type(enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
int chan = util_format_get_first_non_void_channel(format);
if (chan == -1 || desc->channel[chan].type == UTIL_FORMAT_TYPE_FLOAT) {
return V_028C70_NUMBER_FLOAT;
} else {
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
return V_028C70_NUMBER_SRGB;
} else if (desc->channel[chan].type == UTIL_FORMAT_TYPE_SIGNED) {
return desc->channel[chan].pure_integer ? V_028C70_NUMBER_SINT : V_028C70_NUMBER_SNORM;
} else if (desc->channel[chan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
return desc->channel[chan].pure_integer ? V_028C70_NUMBER_UINT : V_028C70_NUMBER_UNORM;
} else {
return V_028C70_NUMBER_UNORM;
}
}
}
unsigned ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
#define HAS_SIZE(x, y, z, w) \
(desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
desc->channel[2].size == (z) && desc->channel[3].size == (w))
if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
return V_028C70_COLOR_10_11_11;
if (gfx_level >= GFX10_3 &&
format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
return V_028C70_COLOR_5_9_9_9;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return V_028C70_COLOR_INVALID;
/* hw cannot support mixed formats (except depth/stencil, since
* stencil is not written to). */
if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
return V_028C70_COLOR_INVALID;
int first_non_void = util_format_get_first_non_void_channel(format);
/* Reject SCALED formats because we don't implement them for CB. */
if (first_non_void >= 0 && first_non_void <= 3 &&
(desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED ||
desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_SIGNED) &&
!desc->channel[first_non_void].normalized &&
!desc->channel[first_non_void].pure_integer)
return V_028C70_COLOR_INVALID;
switch (desc->nr_channels) {
case 1:
switch (desc->channel[0].size) {
case 8:
return V_028C70_COLOR_8;
case 16:
return V_028C70_COLOR_16;
case 32:
return V_028C70_COLOR_32;
case 64:
return V_028C70_COLOR_32_32;
}
break;
case 2:
if (desc->channel[0].size == desc->channel[1].size) {
switch (desc->channel[0].size) {
case 8:
return V_028C70_COLOR_8_8;
case 16:
return V_028C70_COLOR_16_16;
case 32:
return V_028C70_COLOR_32_32;
}
} else if (HAS_SIZE(8, 24, 0, 0)) {
return V_028C70_COLOR_24_8;
} else if (HAS_SIZE(24, 8, 0, 0)) {
return V_028C70_COLOR_8_24;
}
break;
case 3:
if (HAS_SIZE(5, 6, 5, 0)) {
return V_028C70_COLOR_5_6_5;
} else if (HAS_SIZE(32, 8, 24, 0)) {
return V_028C70_COLOR_X24_8_32_FLOAT;
}
break;
case 4:
if (desc->channel[0].size == desc->channel[1].size &&
desc->channel[0].size == desc->channel[2].size &&
desc->channel[0].size == desc->channel[3].size) {
switch (desc->channel[0].size) {
case 4:
return V_028C70_COLOR_4_4_4_4;
case 8:
return V_028C70_COLOR_8_8_8_8;
case 16:
return V_028C70_COLOR_16_16_16_16;
case 32:
return V_028C70_COLOR_32_32_32_32;
}
} else if (HAS_SIZE(5, 5, 5, 1)) {
return V_028C70_COLOR_1_5_5_5;
} else if (HAS_SIZE(1, 5, 5, 5)) {
return V_028C70_COLOR_5_5_5_1;
} else if (HAS_SIZE(10, 10, 10, 2)) {
return V_028C70_COLOR_2_10_10_10;
} else if (HAS_SIZE(2, 10, 10, 10)) {
return V_028C70_COLOR_10_10_10_2;
}
break;
}
return V_028C70_COLOR_INVALID;
}

2
src/amd/common/ac_surface.h
View File

@ -509,8 +509,6 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level,
const struct radeon_surf *surf);
unsigned ac_get_cb_number_type(enum pipe_format format);
unsigned ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format);
#ifdef AC_SURFACE_INCLUDE_NIR
nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info,

2
src/amd/vulkan/radv_sdma.c
View File

@ -14,6 +14,8 @@
#include "radv_cs.h"
#include "radv_formats.h"
#include "ac_formats.h"
struct radv_sdma_chunked_copy_info {
unsigned extent_horizontal_blocks;
unsigned extent_vertical_blocks;

2
src/gallium/drivers/radeonsi/si_sdma_copy_image.c
View File

@ -8,7 +8,7 @@
#include "si_build_pm4.h"
#include "sid.h"
#include "util/u_memory.h"
#include "ac_formats.h"
static
bool si_prepare_for_sdma_copy(struct si_context *sctx, struct si_texture *dst,struct si_texture *src)