mirror of https://gitlab.freedesktop.org/mesa/mesa
mesa: guard better when building with sse4.1 optimisations
When the compiler is not capable/does not accept -msse4.1 while the target has the instruction set we'll blow up as _mesa_streaming_load_memcpy is going to be undefined. To make sure that never happens, wrap the runtime cpu check+caller in an ifdef thus do not compile that hunk of the code. Fix the android build by enabling the optimisation and adding the define where applicable. v2: autoconf conditionals end with "fi" rather than endif. v3: Wrap the definition and call to intel_miptree_{un,}map_movntdqa in if defined(USE_SSE41). Spotted by Matt. Cc: Matt Turner <mattst88@gmail.com> Cc: Adrian Negreanu <adrian.m.negreanu@intel.com> Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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b3121bfd41
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@ -235,6 +235,9 @@ dnl
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dnl Optional flags, check for compiler support
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dnl
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AX_CHECK_COMPILE_FLAG([-msse4.1], [SSE41_SUPPORTED=1], [SSE41_SUPPORTED=0])
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if test "x$SSE41_SUPPORTED" = x1; then
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DEFINES="$DEFINES -DUSE_SSE41"
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fi
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AM_CONDITIONAL([SSE41_SUPPORTED], [test x$SSE41_SUPPORTED = x1])
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dnl
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@ -50,6 +50,7 @@ endif # MESA_ENABLE_ASM
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ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
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LOCAL_SRC_FILES += \
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$(SRCDIR)main/streaming-load-memcpy.c
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LOCAL_CFLAGS := -msse4.1
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endif
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LOCAL_C_INCLUDES := \
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@ -35,6 +35,11 @@ include $(LOCAL_PATH)/Makefile.sources
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LOCAL_CFLAGS := \
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$(MESA_DRI_CFLAGS)
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ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
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LOCAL_CFLAGS += \
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-DUSE_SSE41
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endif
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LOCAL_C_INCLUDES := \
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$(i965_INCLUDES) \
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$(MESA_DRI_C_INCLUDES) \
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@ -1843,6 +1843,7 @@ intel_miptree_unmap_blit(struct brw_context *brw,
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/**
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* "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
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*/
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#if defined(USE_SSE41)
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static void
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intel_miptree_map_movntdqa(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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@ -1910,6 +1911,7 @@ intel_miptree_unmap_movntdqa(struct brw_context *brw,
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map->buffer = NULL;
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map->ptr = NULL;
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}
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#endif
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static void
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intel_miptree_map_s8(struct brw_context *brw,
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@ -2290,8 +2292,10 @@ intel_miptree_map(struct brw_context *brw,
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mt->bo->size >= brw->max_gtt_map_object_size) {
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assert(can_blit_slice(mt, level, slice));
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intel_miptree_map_blit(brw, mt, map, level, slice);
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#if defined(USE_SSE41)
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} else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
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intel_miptree_map_movntdqa(brw, mt, map, level, slice);
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#endif
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} else {
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intel_miptree_map_gtt(brw, mt, map, level, slice);
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}
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@ -2328,8 +2332,10 @@ intel_miptree_unmap(struct brw_context *brw,
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intel_miptree_unmap_depthstencil(brw, mt, map, level, slice);
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} else if (map->mt) {
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intel_miptree_unmap_blit(brw, mt, map, level, slice);
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#if defined(USE_SSE41)
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} else if (map->buffer && cpu_has_sse4_1) {
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intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);
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#endif
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} else {
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intel_miptree_unmap_gtt(brw, mt, map, level, slice);
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}
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