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intel/blorp: add fast clear rectangle dimensions for single sampled TILE64 CCS surfaces 

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23030>
This commit is contained in:
Rohan Garg 2023-01-23 18:25:58 +01:00 committed by Marge Bot
parent 8670fd6ac4
commit afb63443a0
1 changed files with 32 additions and 3 deletions
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35
src/intel/blorp/blorp_clear.c
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@ -211,7 +211,6 @@ get_fast_clear_rect(const struct isl_device *dev,
/* Only single sampled surfaces need to (and actually can) be resolved. */
if (surf->samples == 1) {
if (dev->info->verx10 >= 125) {
assert(surf->tiling == ISL_TILING_4);
/* From Bspec 47709, "MCS/CCS Buffer for Render Target(s)":
*
* SW must ensure that clearing rectangle dimensions cover the
@ -223,8 +222,38 @@ get_fast_clear_rect(const struct isl_device *dev,
* for both alignment and scaling down.
*/
const uint32_t bs = isl_format_get_layout(surf->format)->bpb / 8;
x_align = x_scaledown = 1024 / bs;
y_align = y_scaledown = 16;
if (surf->tiling == ISL_TILING_4) {
x_align = x_scaledown = 1024 / bs;
y_align = y_scaledown = 16;
} else if (surf->tiling == ISL_TILING_64) {
switch (bs) {
case 1:
x_align = x_scaledown = 128;
y_align = y_scaledown = 128;
break;
case 2:
x_align = x_scaledown = 128;
y_align = y_scaledown = 64;
break;
case 4:
x_align = x_scaledown = 64;
y_align = y_scaledown = 64;
break;
case 8:
x_align = x_scaledown = 64;
y_align = y_scaledown = 32;
break;
case 16:
x_align = x_scaledown = 32;
y_align = y_scaledown = 32;
break;
default:
unreachable("unsupported bpp");
}
} else {
unreachable("Unsupported tiling format");
}
} else {
assert(aux_surf->usage == ISL_SURF_USAGE_CCS_BIT);
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render