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intel/brw: update Xe2 max SIMD message sizes 

All the non-transpose messages are SIMD 1,2,4,8,16,32 capable (BSpec
57330)

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29212>
This commit is contained in:
Rohan Garg 2024-03-04 11:44:05 +01:00 committed by Marge Bot
parent c8852719d0
commit aa9244c8f6
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_fs_lower_simd_width.cpp
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@ -394,7 +394,7 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
return 8;
return devinfo->ver < 20 ? 8 : inst->exec_size;
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL: