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Code Issues 9 Packages Projects Releases Wiki Activity

intel/brw: fix subgroup size of geometry stages for lnl+ 

Fixes dEQP-VK.subgroups.size_control.*allow_varying_subgroup_size* and
maybe others checking subgroup size.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29177>
This commit is contained in:
Iván Briano 2024-05-07 12:38:36 -07:00 committed by Marge Bot
parent a28a289374
commit a9f24fb5f1
6 changed files with 18 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/intel/compiler/brw_compile_gs.cpp
View File

@ -58,7 +58,8 @@ brw_compile_gs(const struct brw_compiler *compiler,
&c.input_vue_map, inputs_read,
nir->info.separate_shader, 1);
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_apply_key(nir, compiler, &key->base,
brw_geometry_stage_dispatch_width(compiler->devinfo));
brw_nir_lower_vue_inputs(nir, &c.input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, debug_enabled,

3
src/intel/compiler/brw_compile_tcs.cpp
View File

@ -65,7 +65,8 @@ brw_compile_tcs(const struct brw_compiler *compiler,
nir->info.outputs_written,
nir->info.patch_outputs_written);
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_apply_key(nir, compiler, &key->base,
brw_geometry_stage_dispatch_width(compiler->devinfo));
brw_nir_lower_vue_inputs(nir, &input_vue_map);
brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map,
key->_tes_primitive_mode);

3
src/intel/compiler/brw_compile_vs.cpp
View File

@ -26,7 +26,8 @@ brw_compile_vs(const struct brw_compiler *compiler,
prog_data->base.base.ray_queries = nir->info.ray_queries;
prog_data->base.base.total_scratch = 0;
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_apply_key(nir, compiler, &key->base,
brw_geometry_stage_dispatch_width(compiler->devinfo));
prog_data->inputs_read = nir->info.inputs_read;
prog_data->double_inputs_read = nir->info.vs.double_inputs;

2
src/intel/compiler/brw_private.h
View File

@ -78,6 +78,8 @@ inline bool brw_simd_any_compiled(const brw_simd_selection_state &state)
return brw_simd_first_compiled(state) >= 0;
}
unsigned brw_geometry_stage_dispatch_width(const struct intel_device_info *devinfo);
bool brw_simd_should_compile(brw_simd_selection_state &state, unsigned simd);
void brw_simd_mark_compiled(brw_simd_selection_state &state, unsigned simd, bool spilled);

3
src/intel/compiler/brw_shader.cpp
View File

@ -624,7 +624,8 @@ brw_compile_tes(const struct brw_compiler *compiler,
nir->info.inputs_read = key->inputs_read;
nir->info.patch_inputs_read = key->patch_inputs_read;
brw_nir_apply_key(nir, compiler, &key->base, 8);
brw_nir_apply_key(nir, compiler, &key->base,
brw_geometry_stage_dispatch_width(compiler->devinfo));
brw_nir_lower_tes_inputs(nir, input_vue_map);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, debug_enabled,

8
src/intel/compiler/brw_simd_selection.cpp
View File

@ -41,6 +41,14 @@ brw_required_dispatch_width(const struct shader_info *info)
}
}
unsigned
brw_geometry_stage_dispatch_width(const struct intel_device_info *devinfo)
{
if (devinfo->ver >= 20)
return 16;
return 8;
}
static inline bool
test_bit(unsigned mask, unsigned bit) {
return mask & (1u << bit);