mirror of https://gitlab.freedesktop.org/mesa/mesa
intel/brw: Fix generate_mov_indirect to check has_64bit_int not float
We are overriding the type to Q/UQ, so we need to split to two MOVs if 64-bit integer math is not supported. For reference, Meteorlake does support 64-bit floats but would still not work correctly here. See also brw_broadcast(), which does similar indirects but correctly checks has_64bit_int instead of has_64bit_float. Cc: mesa-stable Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28458>
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@ -304,7 +304,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
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reg.nr = imm_byte_offset / REG_SIZE;
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reg.subnr = imm_byte_offset % REG_SIZE;
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if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
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if (type_sz(reg.type) > 4 && !devinfo->has_64bit_int) {
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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subscript(reg, BRW_REGISTER_TYPE_D, 0));
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brw_set_default_swsb(p, tgl_swsb_null());
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@ -379,8 +379,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
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brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
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if (type_sz(reg.type) > 4 &&
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(intel_device_info_is_9lp(devinfo) ||
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!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
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(intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) {
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/* IVB has an issue (which we found empirically) where it reads two
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* address register components per channel for indirectly addressed
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* 64-bit sources.
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