mirror of https://gitlab.freedesktop.org/mesa/mesa
intel: Add SUPPORT_INTEL_INTEGRATED_GPUS build argument
This is meant to remove any integrated GPU only code paths that can't be compiled in CPU architectures different than x86. Discrete GPUS don't have need_clflush set to true so it was just matter of remove some code blocks around need_clflush but was left a check in anv_physical_device_init_heaps() to fail physical device initialization if it ever became false. Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19812>
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@ -1572,6 +1572,11 @@ elif with_intel_vk or with_intel_hasvk
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error('Intel "Anvil" Vulkan driver requires the dl_iterate_phdr function')
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endif
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# only used in Iris and ANV
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if with_any_intel and ['x86', 'x86_64'].contains(host_machine.cpu_family())
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pre_args += '-DSUPPORT_INTEL_INTEGRATED_GPUS'
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endif
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# Determine whether or not the rt library is needed for time functions
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if host_machine.system() == 'windows' or cc.has_function('clock_gettime')
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dep_clock = null_dep
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@ -27,6 +27,7 @@
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#define CACHELINE_SIZE 64
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#define CACHELINE_MASK 63
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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static inline void
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intel_clflush_range(void *start, size_t size)
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{
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@ -67,5 +68,6 @@ intel_invalidate_range(void *start, size_t size)
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__builtin_ia32_clflush(start + size - 1);
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__builtin_ia32_mfence();
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}
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#endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
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#endif
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@ -185,11 +185,13 @@ padding_is_good(int fd, uint32_t handle)
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}
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mapped = (uint8_t*) (uintptr_t) mmap_arg.addr_ptr;
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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/* bah-humbug, we need to see the latest contents and
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* if the bo is not cache coherent we likely need to
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* invalidate the cache lines to get it.
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*/
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intel_invalidate_range(mapped, PADDING_SIZE);
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#endif
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expected_value = handle & 0xFF;
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for (uint32_t i = 0; i < PADDING_SIZE; ++i) {
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@ -388,8 +388,10 @@ anv_batch_bo_link(struct anv_cmd_buffer *cmd_buffer,
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uint64_t *map = prev_bbo->bo->map + bb_start_offset + 4;
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*map = intel_canonical_address(next_bbo->bo->offset + next_bbo_offset);
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (cmd_buffer->device->physical->memory.need_clflush)
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intel_flush_range(map, sizeof(uint64_t));
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#endif
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}
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static void
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@ -1508,6 +1510,7 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf,
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first_batch_bo->bo->exec_obj_index = last_idx;
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}
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (device->physical->memory.need_clflush) {
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__builtin_ia32_mfence();
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struct anv_batch_bo **bbo;
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@ -1518,6 +1521,7 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf,
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}
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}
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}
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#endif
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execbuf->execbuf = (struct drm_i915_gem_execbuffer2) {
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.buffers_ptr = (uintptr_t) execbuf->objects,
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@ -1594,8 +1598,10 @@ setup_utrace_execbuf(struct anv_execbuf *execbuf, struct anv_queue *queue,
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flush->batch_bo->exec_obj_index = last_idx;
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}
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (device->physical->memory.need_clflush)
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intel_flush_range(flush->batch_bo->map, flush->batch_bo->size);
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#endif
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execbuf->execbuf = (struct drm_i915_gem_execbuffer2) {
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.buffers_ptr = (uintptr_t) execbuf->objects,
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@ -2064,8 +2070,10 @@ anv_queue_submit_simple_batch(struct anv_queue *queue,
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return result;
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memcpy(batch_bo->map, batch->start, batch_size);
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (device->physical->memory.need_clflush)
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intel_flush_range(batch_bo->map, batch_size);
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#endif
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if (INTEL_DEBUG(DEBUG_BATCH)) {
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intel_print_batch(&device->decoder_ctx,
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@ -535,12 +535,16 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd)
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};
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}
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device->memory.need_clflush = false;
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for (unsigned i = 0; i < device->memory.type_count; i++) {
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VkMemoryPropertyFlags props = device->memory.types[i].propertyFlags;
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if ((props & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) &&
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!(props & VK_MEMORY_PROPERTY_HOST_COHERENT_BIT))
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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device->memory.need_clflush = true;
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#else
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return vk_errorf(device, VK_ERROR_INITIALIZATION_FAILED,
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"Memory configuration requires flushing, but it's not implemented for this architecture");
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#endif
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}
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return VK_SUCCESS;
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@ -3023,8 +3027,10 @@ anv_device_init_trivial_batch(struct anv_device *device)
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anv_batch_emit(&batch, GFX7_MI_BATCH_BUFFER_END, bbe);
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anv_batch_emit(&batch, GFX7_MI_NOOP, noop);
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (device->physical->memory.need_clflush)
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intel_clflush_range(batch.start, batch.next - batch.start);
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#endif
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return VK_SUCCESS;
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}
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@ -4392,6 +4398,7 @@ VkResult anv_FlushMappedMemoryRanges(
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uint32_t memoryRangeCount,
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const VkMappedMemoryRange* pMemoryRanges)
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{
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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ANV_FROM_HANDLE(anv_device, device, _device);
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if (!device->physical->memory.need_clflush)
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@ -4413,7 +4420,7 @@ VkResult anv_FlushMappedMemoryRanges(
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MIN2(pMemoryRanges[i].size,
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mem->map_size - map_offset));
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}
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#endif
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return VK_SUCCESS;
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}
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@ -4422,6 +4429,7 @@ VkResult anv_InvalidateMappedMemoryRanges(
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uint32_t memoryRangeCount,
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const VkMappedMemoryRange* pMemoryRanges)
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{
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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ANV_FROM_HANDLE(anv_device, device, _device);
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if (!device->physical->memory.need_clflush)
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@ -4443,7 +4451,7 @@ VkResult anv_InvalidateMappedMemoryRanges(
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/* Make sure no reads get moved up above the invalidate. */
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__builtin_ia32_mfence();
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#endif
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return VK_SUCCESS;
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}
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@ -1019,7 +1019,9 @@ struct anv_physical_device {
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struct anv_memory_type types[VK_MAX_MEMORY_TYPES];
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uint32_t heap_count;
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struct anv_memory_heap heaps[VK_MAX_MEMORY_HEAPS];
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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bool need_clflush;
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#endif
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} memory;
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/* Either we have a single vram region and it's all mappable, or we have
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@ -97,10 +97,12 @@ VkResult anv_QueuePresentKHR(
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if (device->debug_frame_desc) {
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device->debug_frame_desc->frame_id++;
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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if (device->physical->memory.need_clflush) {
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intel_clflush_range(device->debug_frame_desc,
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sizeof(*device->debug_frame_desc));
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}
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#endif
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}
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result = vk_queue_wait_before_present(&queue->vk, pPresentInfo);
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