mirror of https://gitlab.freedesktop.org/mesa/mesa
ac/nir/ngg: Enable packing 16-bit mesh shader outputs.
This prepares ac_nir_lower_ngg_ms for the possibility of packing two 16-bit outputs into the same 32-bit output slot, by handling the high_16bits flag in NIR IO semantics. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28704>
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@ -3824,9 +3824,12 @@ ms_store_arrayed_output(nir_builder *b,
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const ms_out_part *out = ms_get_out_layout_part(io_sem.location, &b->shader->info, &out_mode, s);
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update_ms_output_info(io_sem, base_off_src, write_mask, component_offset, store_val->bit_size, out, s);
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bool hi_16b = io_sem.high_16bits;
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bool lo_16b = !hi_16b && store_val->bit_size == 16;
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unsigned mapped_location = util_bitcount64(out->mask & u_bit_consecutive64(0, io_sem.location));
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unsigned num_outputs = util_bitcount64(out->mask);
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unsigned const_off = out->addr + component_offset * 4;
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unsigned const_off = out->addr + component_offset * 4 + (hi_16b ? 2 : 0);
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nir_def *base_addr = ms_arrayed_output_base_addr(b, arr_index, mapped_location, num_outputs);
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nir_def *base_offset = base_off_src->ssa;
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@ -3873,6 +3876,17 @@ ms_store_arrayed_output(nir_builder *b,
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u_foreach_bit(comp, write_mask_32) {
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nir_def *val = nir_channel(b, store_val, comp);
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unsigned idx = io_sem.location * 4 + comp + component_offset;
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if (lo_16b) {
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nir_def *v = nir_channel(b, nir_load_var(b, s->out_variables[idx]), comp + component_offset);
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nir_def *var_hi = nir_unpack_32_2x16_split_y(b, v);
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val = nir_pack_32_2x16_split(b, val, var_hi);
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} else if (hi_16b) {
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nir_def *v = nir_channel(b, nir_load_var(b, s->out_variables[idx]), comp + component_offset);
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nir_def *var_lo = nir_unpack_32_2x16_split_x(b, v);
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val = nir_pack_32_2x16_split(b, var_lo, val);
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}
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nir_store_var(b, s->out_variables[idx], val, 0x1);
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}
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} else {
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