mirror of https://gitlab.freedesktop.org/mesa/mesa
intel/brw: Drop align16 support in brw_broadcast()
align16 support is only used on Gen9 for 3-source instructions, quad swizzling, and dPdy calculations. We don't need it for broadcast. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28458>
This commit is contained in:
Kenneth Graunke
Marge Bot
parent
a520c976a5
commit
9e0d0190ea
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@ -1957,12 +1957,11 @@ brw_broadcast(struct brw_codegen *p,
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struct brw_reg idx)
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{
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const struct intel_device_info *devinfo = p->devinfo;
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const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
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brw_inst *inst;
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assert(brw_get_default_access_mode(p) == BRW_ALIGN_1);
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brw_push_insn_state(p);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_set_default_exec_size(p, align1 ? BRW_EXECUTE_1 : BRW_EXECUTE_4);
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brw_set_default_exec_size(p, BRW_EXECUTE_1);
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assert(src.file == BRW_GENERAL_REGISTER_FILE &&
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src.address_mode == BRW_ADDRESS_DIRECT);
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@ -1980,15 +1979,14 @@ brw_broadcast(struct brw_codegen *p,
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src.type = dst.type = brw_reg_type_from_bit_size(type_sz(src.type) * 8,
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BRW_REGISTER_TYPE_UD);
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if ((src.vstride == 0 && (src.hstride == 0 || !align1)) ||
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if ((src.vstride == 0 && src.hstride == 0) ||
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idx.file == BRW_IMMEDIATE_VALUE) {
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/* Trivial, the source is already uniform or the index is a constant.
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* We will typically not get here if the optimizer is doing its job, but
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* asserting would be mean.
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*/
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const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
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src = align1 ? stride(suboffset(src, i), 0, 1, 0) :
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stride(suboffset(src, 4 * i), 0, 4, 1);
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src = stride(suboffset(src, i), 0, 1, 0);
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if (type_sz(src.type) > 4 && !devinfo->has_64bit_int) {
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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@ -2014,83 +2012,64 @@ brw_broadcast(struct brw_codegen *p,
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*/
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assert(src.subnr == 0);
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if (align1) {
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const struct brw_reg addr =
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retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
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unsigned offset = src.nr * REG_SIZE + src.subnr;
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/* Limit in bytes of the signed indirect addressing immediate. */
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const unsigned limit = 512;
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const struct brw_reg addr =
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retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD);
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unsigned offset = src.nr * REG_SIZE + src.subnr;
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/* Limit in bytes of the signed indirect addressing immediate. */
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const unsigned limit = 512;
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brw_push_insn_state(p);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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brw_set_default_flag_reg(p, 0, 0);
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brw_push_insn_state(p);
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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brw_set_default_flag_reg(p, 0, 0);
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/* Take into account the component size and horizontal stride. */
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assert(src.vstride == src.hstride + src.width);
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brw_SHL(p, addr, vec1(idx),
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brw_imm_ud(util_logbase2(type_sz(src.type)) +
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src.hstride - 1));
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/* We can only address up to limit bytes using the indirect
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* addressing immediate, account for the difference if the source
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* register is above this limit.
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*/
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if (offset >= limit) {
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brw_set_default_swsb(p, tgl_swsb_regdist(1));
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brw_ADD(p, addr, addr, brw_imm_ud(offset - offset % limit));
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offset = offset % limit;
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}
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brw_pop_insn_state(p);
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/* Take into account the component size and horizontal stride. */
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assert(src.vstride == src.hstride + src.width);
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brw_SHL(p, addr, vec1(idx),
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brw_imm_ud(util_logbase2(type_sz(src.type)) +
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src.hstride - 1));
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/* We can only address up to limit bytes using the indirect
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* addressing immediate, account for the difference if the source
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* register is above this limit.
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*/
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if (offset >= limit) {
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brw_set_default_swsb(p, tgl_swsb_regdist(1));
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brw_ADD(p, addr, addr, brw_imm_ud(offset - offset % limit));
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offset = offset % limit;
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}
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/* Use indirect addressing to fetch the specified component. */
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if (type_sz(src.type) > 4 &&
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(intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) {
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/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
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*
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* "When source or destination datatype is 64b or operation is
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* integer DWord multiply, indirect addressing must not be
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* used."
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*
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* We may also not support Q/UQ types.
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*
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* To work around both of these, we do two integer MOVs instead
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* of one 64-bit MOV. Because no double value should ever cross
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* a register boundary, it's safe to use the immediate offset in
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* the indirect here to handle adding 4 bytes to the offset and
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* avoid the extra ADD to the register file.
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*/
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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retype(brw_vec1_indirect(addr.subnr, offset),
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BRW_REGISTER_TYPE_D));
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brw_set_default_swsb(p, tgl_swsb_null());
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
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retype(brw_vec1_indirect(addr.subnr, offset + 4),
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BRW_REGISTER_TYPE_D));
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} else {
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brw_MOV(p, dst,
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retype(brw_vec1_indirect(addr.subnr, offset), src.type));
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}
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} else {
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/* In SIMD4x2 mode the index can be either zero or one, replicate it
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* to all bits of a flag register,
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brw_pop_insn_state(p);
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brw_set_default_swsb(p, tgl_swsb_regdist(1));
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/* Use indirect addressing to fetch the specified component. */
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if (type_sz(src.type) > 4 &&
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(intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) {
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/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
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*
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* "When source or destination datatype is 64b or operation is
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* integer DWord multiply, indirect addressing must not be
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* used."
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*
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* We may also not support Q/UQ types.
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*
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* To work around both of these, we do two integer MOVs instead
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* of one 64-bit MOV. Because no double value should ever cross
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* a register boundary, it's safe to use the immediate offset in
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* the indirect here to handle adding 4 bytes to the offset and
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* avoid the extra ADD to the register file.
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*/
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inst = brw_MOV(p,
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brw_null_reg(),
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stride(brw_swizzle(idx, BRW_SWIZZLE_XXXX), 4, 4, 1));
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brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NONE);
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brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_NZ);
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brw_inst_set_flag_reg_nr(devinfo, inst, 1);
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/* and use predicated SEL to pick the right channel. */
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inst = brw_SEL(p, dst,
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stride(suboffset(src, 4), 4, 4, 1),
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stride(src, 4, 4, 1));
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brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NORMAL);
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brw_inst_set_flag_reg_nr(devinfo, inst, 1);
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
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retype(brw_vec1_indirect(addr.subnr, offset),
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BRW_REGISTER_TYPE_D));
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brw_set_default_swsb(p, tgl_swsb_null());
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brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
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retype(brw_vec1_indirect(addr.subnr, offset + 4),
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BRW_REGISTER_TYPE_D));
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} else {
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brw_MOV(p, dst,
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retype(brw_vec1_indirect(addr.subnr, offset), src.type));
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}
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}
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