intel/nir: add printf lowering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25814>

docs/envvars.rst

@@ -594,6 +594,9 @@ Intel driver environment variables
    ``sf``
       emit messages about the strips & fans unit (for old gens, includes
       the SF program)
+   ``shader-print``
+      allow developer print traces added by `brw_nir_printf` to be
+      printed out on the console
    ``soft64``
       enable implementation of software 64bit floating point support
    ``sparse``

src/intel/compiler/brw_compiler.h

@@ -461,6 +461,9 @@ enum brw_shader_reloc_id {
    BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE,
    BRW_SHADER_RELOC_LAST_EMBEDDED_SAMPLER_HANDLE =
    BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE + BRW_MAX_EMBEDDED_SAMPLERS - 1,
+   BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_LOW,
+   BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_HIGH,
+   BRW_SHADER_RELOC_PRINTF_BASE_IDENTIFIER,
 };
 
 enum brw_shader_reloc_type {

src/intel/compiler/brw_nir.c

@@ -1647,6 +1647,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
 
    OPT(nir_opt_combine_barriers, combine_all_memory_barriers, NULL);
 
+   OPT(intel_nir_lower_printf);
+
    do {
       progress = false;
       OPT(nir_opt_algebraic_before_ffma);
@@ -2171,4 +2173,3 @@ brw_nir_get_var_type(const struct nir_shader *nir, nir_variable *var)
 
    return type;
 }
-

src/intel/compiler/brw_nir.h

@@ -265,6 +265,9 @@ brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
    return indirect_mask;
 }
 
+void
+brw_nir_printf(nir_builder *b, const char *fmt, ...);
+
 #ifdef __cplusplus
 }
 #endif

src/intel/compiler/intel_nir.h

@@ -40,6 +40,8 @@ bool intel_nir_opt_peephole_imul32x16(nir_shader *shader);
 
 bool intel_nir_pulls_at_sample(nir_shader *shader);
 
+bool intel_nir_lower_printf(nir_shader *nir);
+
 #ifdef __cplusplus
 }
 #endif

src/intel/compiler/intel_nir_lower_printf.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "intel_nir.h"
+#include "compiler/nir/nir_builder.h"
+#include "brw_compiler.h"
+
+static bool
+lower_printf_intrinsics(nir_builder *b, nir_instr *instr, void *cb_data)
+{
+   if (instr->type != nir_instr_type_intrinsic)
+      return false;
+
+   b->cursor = nir_before_instr(instr);
+
+   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+   switch (intrin->intrinsic) {
+   case nir_intrinsic_load_printf_buffer_address:
+      nir_def_rewrite_uses(
+         &intrin->def,
+         nir_pack_64_2x32_split(
+            b,
+            nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_LOW),
+            nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BUFFER_ADDR_HIGH)));
+      nir_instr_remove(instr);
+      return true;
+
+   case nir_intrinsic_load_printf_base_identifier:
+      nir_def_rewrite_uses(
+         &intrin->def,
+         nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_PRINTF_BASE_IDENTIFIER));
+      nir_instr_remove(instr);
+      return true;
+
+   default:
+      return false;
+   }
+}
+
+bool
+intel_nir_lower_printf(nir_shader *nir)
+{
+   return nir_shader_instructions_pass(nir, lower_printf_intrinsics,
+                                       nir_metadata_block_index |
+                                       nir_metadata_dominance,
+                                       NULL);
+}

src/intel/compiler/meson.build

@@ -28,6 +28,7 @@ intel_nir_files = files(
   'intel_nir_lower_conversions.c',
   'intel_nir_lower_non_uniform_barycentric_at_sample.c',
   'intel_nir_lower_non_uniform_resource_intel.c',
+  'intel_nir_lower_printf.c',
   'intel_nir_lower_shading_rate_output.c',
   'intel_nir_lower_sparse.c',
   'intel_nir_lower_texture.c',

src/intel/dev/intel_debug.c

@@ -106,6 +106,7 @@ static const struct debug_control debug_control[] = {
    { "draw_bkp",    DEBUG_DRAW_BKP },
    { "bat-stats",   DEBUG_BATCH_STATS },
    { "reg-pressure", DEBUG_REG_PRESSURE },
+   { "shader-print", DEBUG_SHADER_PRINT },
    { NULL,    0 }
 };
 

src/intel/dev/intel_debug.h

@@ -97,6 +97,7 @@ extern uint64_t intel_debug;
 #define DEBUG_DRAW_BKP            (1ull << 49)
 #define DEBUG_BATCH_STATS         (1ull << 50)
 #define DEBUG_REG_PRESSURE        (1ull << 51)
+#define DEBUG_SHADER_PRINT        (1ull << 52)
 
 #define DEBUG_ANY                 (~0ull)