mirror of https://gitlab.freedesktop.org/mesa/mesa
intel/disasm: Fix cache load/store disassembly for URB messages
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28868>
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@ -2254,6 +2254,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
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case LSC_OP_LOAD:
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format(file, ",");
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err |= control(file, "cache_load",
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devinfo->ver >= 20 ?
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xe2_lsc_cache_load :
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lsc_cache_load,
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lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
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&space);
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@ -2261,6 +2263,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
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default:
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format(file, ",");
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err |= control(file, "cache_store",
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devinfo->ver >= 20 ?
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xe2_lsc_cache_store :
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lsc_cache_store,
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lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
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&space);
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