mirror of https://gitlab.freedesktop.org/mesa/mesa
ac/nir/esgs: Slightly refactor emitting IO loads and stores.
No functional changes, just reorganize the code a little bit in preparation for the next commits. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28768>
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@ -37,8 +37,8 @@ typedef struct {
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} lower_esgs_io_state;
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static nir_def *
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emit_split_buffer_load(nir_builder *b, nir_def *desc, nir_def *v_off, nir_def *s_off,
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unsigned component_stride, unsigned num_components, unsigned bit_size)
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emit_split_buffer_load(nir_builder *b, unsigned num_components, unsigned bit_size,
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unsigned component_stride, nir_def *desc, nir_def *v_off, nir_def *s_off)
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{
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unsigned total_bytes = num_components * bit_size / 8u;
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unsigned full_dwords = total_bytes / 4u;
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@ -71,8 +71,7 @@ emit_split_buffer_load(nir_builder *b, nir_def *desc, nir_def *v_off, nir_def *s
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static void
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emit_split_buffer_store(nir_builder *b, nir_def *d, nir_def *desc, nir_def *v_off, nir_def *s_off,
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unsigned component_stride, unsigned num_components, unsigned bit_size,
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unsigned writemask, bool swizzled, bool slc)
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unsigned bit_size, unsigned const_offset, unsigned writemask, bool swizzled, bool slc)
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{
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nir_def *zero = nir_imm_int(b, 0);
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@ -93,7 +92,7 @@ emit_split_buffer_store(nir_builder *b, nir_def *d, nir_def *desc, nir_def *v_of
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nir_def *store_val = nir_extract_bits(b, &d, 1, start_byte * 8u, 1, store_bytes * 8u);
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nir_store_buffer_amd(b, store_val, desc, v_off, s_off, zero,
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.base = start_byte, .memory_modes = nir_var_shader_out,
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.base = start_byte + const_offset, .memory_modes = nir_var_shader_out,
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.access = ACCESS_COHERENT |
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(slc ? ACCESS_NON_TEMPORAL : 0) |
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(swizzled ? ACCESS_IS_SWIZZLED_AMD : 0));
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@ -138,30 +137,31 @@ lower_es_output_store(nir_builder *b,
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*
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* So writes to those outputs in ES are simply ignored.
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*/
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unsigned semantic = nir_intrinsic_io_semantics(intrin).location;
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if (semantic == VARYING_SLOT_LAYER || semantic == VARYING_SLOT_VIEWPORT) {
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const nir_io_semantics io_sem = nir_intrinsic_io_semantics(intrin);
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if (io_sem.location == VARYING_SLOT_LAYER || io_sem.location == VARYING_SLOT_VIEWPORT) {
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nir_instr_remove(&intrin->instr);
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return true;
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}
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lower_esgs_io_state *st = (lower_esgs_io_state *) state;
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unsigned write_mask = nir_intrinsic_write_mask(intrin);
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const unsigned write_mask = nir_intrinsic_write_mask(intrin);
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b->cursor = nir_before_instr(&intrin->instr);
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nir_def *io_off = ac_nir_calc_io_offset(b, intrin, nir_imm_int(b, 16u), 4u, st->map_io);
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nir_def *store_val = intrin->src[0].ssa;
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if (st->gfx_level <= GFX8) {
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/* GFX6-8: ES is a separate HW stage, data is passed from ES to GS in VRAM. */
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nir_def *ring = nir_load_ring_esgs_amd(b);
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nir_def *es2gs_off = nir_load_ring_es2gs_offset_amd(b);
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emit_split_buffer_store(b, intrin->src[0].ssa, ring, io_off, es2gs_off, 4u,
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intrin->src[0].ssa->num_components, intrin->src[0].ssa->bit_size,
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write_mask, true, true);
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emit_split_buffer_store(b, store_val, ring, io_off, es2gs_off,
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store_val->bit_size,
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0, write_mask, true, true);
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} else {
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/* GFX9+: ES is merged into GS, data is passed through LDS. */
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nir_def *vertex_idx = nir_load_local_invocation_index(b);
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nir_def *off = nir_iadd(b, nir_imul_imm(b, vertex_idx, st->esgs_itemsize), io_off);
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nir_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask);
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nir_store_shared(b, store_val, off, .write_mask = write_mask);
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}
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nir_instr_remove(&intrin->instr);
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@ -271,8 +271,8 @@ lower_gs_per_vertex_input_load(nir_builder *b,
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unsigned wave_size = 64u; /* GFX6-8 only support wave64 */
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nir_def *ring = nir_load_ring_esgs_amd(b);
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return emit_split_buffer_load(b, ring, off, nir_imm_zero(b, 1, 32), 4u * wave_size,
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intrin->def.num_components, intrin->def.bit_size);
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return emit_split_buffer_load(b, intrin->def.num_components, intrin->def.bit_size,
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4u * wave_size, ring, off, nir_imm_int(b, 0));
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}
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static bool
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