mirror of https://gitlab.freedesktop.org/mesa/mesa
isl: fix inline c identifier reference -> inline code
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28499>
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@ -2344,8 +2344,8 @@ isl_calc_min_row_pitch(const struct isl_device *dev,
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}
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/**
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* Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
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* size is `bits` bits?
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* Is ``pitch`` in the valid range for a hardware bitfield, if the bitfield's
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* size is ``bits`` bits?
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*
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* Hardware pitch fields are offset by 1. For example, if the size of
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* RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
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@ -58,7 +58,7 @@ struct intel_device_info;
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* Get the hardware generation of isl_device.
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*
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* You can define this as a compile-time constant in the CFLAGS. For example,
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* `gcc -DISL_GFX_VER(dev)=9 ...`.
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* ``gcc -DISL_GFX_VER(dev)=9 ...``.
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*/
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#define ISL_GFX_VER(__dev) ((__dev)->info->ver)
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#define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
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@ -78,7 +78,7 @@ struct intel_device_info;
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* @brief Get the hardware generation of isl_device.
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*
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* You can define this as a compile-time constant in the CFLAGS. For example,
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* `gcc -DISL_GFX_VER(dev)=9 ...`.
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* ``gcc -DISL_GFX_VER(dev)=9 ...``.
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*/
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#define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_HSW)
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#endif
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@ -90,7 +90,7 @@ struct intel_device_info;
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#ifndef ISL_DEV_USE_SEPARATE_STENCIL
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/**
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* You can define this as a compile-time constant in the CFLAGS. For example,
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* `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
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* ``gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...``.
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*/
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#define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
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#define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
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@ -783,14 +783,14 @@ enum isl_aux_usage {
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* main surface which says how the corresponding pair of cache lines in the
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* main surface are to be interpreted. Valid CCS values include:
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*
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* - `0x0`: Indicates that the corresponding pair of cache lines in the
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* - ``0x0``: Indicates that the corresponding pair of cache lines in the
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* main surface contain valid color data
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*
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* - `0x1`: Indicates that the corresponding pair of cache lines in the
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* - ``0x1``: Indicates that the corresponding pair of cache lines in the
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* main surface contain compressed color data. Typically, the
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* compressed data fits in one of the two cache lines.
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*
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* - `0x3`: Indicates that the corresponding pair of cache lines in the
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* - ``0x3``: Indicates that the corresponding pair of cache lines in the
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* main surface should be ignored. Those cache lines should be
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* considered to contain the clear color.
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*
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@ -1243,8 +1243,8 @@ enum isl_msaa_layout {
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* Suppose the multisample surface's logical extent is (w, h) and its
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* sample count is N. Then surface's physical extent is the same as
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* a singlesample 2D surface whose logical extent is (w, h) and array
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* length is N. Array slice `i` contains the pixel values for sample
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* index `i`.
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* length is N. Array slice ``i`` contains the pixel values for sample
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* index ``i``.
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*
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* The Ivybridge docs refer to surfaces in this format as UMS
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* (Uncompressed Multsample Layout) and CMS (Compressed Multisample
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@ -1706,7 +1706,7 @@ struct isl_view {
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* specified in terms of 2-D layers and must be a multiple of 6.
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*
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* 3-D textures are effectively treated as 2-D arrays when used as a
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* storage image or render target. If `usage` contains
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* storage image or render target. If ``usage`` contains
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* ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
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* base_array_layer and array_len are applied. If the surface is only used
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* for texturing, they are ignored.
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