mirror of https://gitlab.freedesktop.org/mesa/mesa
nvk: Use the NAK helpers to fill QMDs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28756>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
9ace83603d
commit
16f2249a80
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@ -26,26 +26,6 @@
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#include "nvk_clc597.h"
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#include "nvk_clc6c0.h"
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#include "drf.h"
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#include "cla0c0qmd.h"
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#include "clc0c0qmd.h"
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#include "clc3c0qmd.h"
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#include "clc6c0qmd.h"
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#define NVA0C0_QMDV00_06_VAL_SET(p,a...) NVVAL_MW_SET((p), NVA0C0, QMDV00_06, ##a)
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#define NVA0C0_QMDV00_06_DEF_SET(p,a...) NVDEF_MW_SET((p), NVA0C0, QMDV00_06, ##a)
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#define NVC0C0_QMDV02_01_VAL_SET(p,a...) NVVAL_MW_SET((p), NVC0C0, QMDV02_01, ##a)
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#define NVC0C0_QMDV02_01_DEF_SET(p,a...) NVDEF_MW_SET((p), NVC0C0, QMDV02_01, ##a)
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#define NVC3C0_QMDV02_02_VAL_SET(p,a...) NVVAL_MW_SET((p), NVC3C0, QMDV02_02, ##a)
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#define NVC3C0_QMDV02_02_DEF_SET(p,a...) NVDEF_MW_SET((p), NVC3C0, QMDV02_02, ##a)
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#define NVC6C0_QMDV03_00_VAL_SET(p,a...) NVVAL_MW_SET((p), NVC6C0, QMDV03_00, ##a)
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#define NVC6C0_QMDV03_00_DEF_SET(p,a...) NVDEF_MW_SET((p), NVC6C0, QMDV03_00, ##a)
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#define QMD_DEF_SET(qmd, class_id, version_major, version_minor, a...) \
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NVDEF_MW_SET((qmd), NV##class_id, QMDV##version_major##_##version_minor, ##a)
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#define QMD_VAL_SET(qmd, class_id, version_major, version_minor, a...) \
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NVVAL_MW_SET((qmd), NV##class_id, QMDV##version_major##_##version_minor, ##a)
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VkResult
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nvk_push_dispatch_state_init(struct nvk_device *dev, struct nv_push *p)
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{
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@ -104,202 +84,6 @@ nvk_cmd_invalidate_compute_state(struct nvk_cmd_buffer *cmd)
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memset(&cmd->state.cs, 0, sizeof(cmd->state.cs));
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}
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static int
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gv100_sm_config_smem_size(uint32_t size)
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{
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if (size > 64 * 1024) size = 96 * 1024;
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else if (size > 32 * 1024) size = 64 * 1024;
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else if (size > 16 * 1024) size = 32 * 1024;
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else if (size > 8 * 1024) size = 16 * 1024;
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else size = 8 * 1024;
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return (size / 4096) + 1;
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}
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#define nvk_qmd_init_base(qmd, shader, class_id, version_major, version_minor) \
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do { \
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QMD_DEF_SET(qmd, class_id, version_major, version_minor, API_VISIBLE_CALL_LIMIT, NO_CHECK); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, BARRIER_COUNT, shader->info.num_barriers); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, CTA_THREAD_DIMENSION0, \
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shader->info.cs.local_size[0]); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, CTA_THREAD_DIMENSION1, \
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shader->info.cs.local_size[1]); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, CTA_THREAD_DIMENSION2, \
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shader->info.cs.local_size[2]); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, QMD_MAJOR_VERSION, version_major); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, QMD_VERSION, version_minor); \
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QMD_DEF_SET(qmd, class_id, version_major, version_minor, SAMPLER_INDEX, INDEPENDENTLY); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, SHADER_LOCAL_MEMORY_LOW_SIZE, \
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align(shader->info.slm_size, 0x10)); \
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QMD_VAL_SET(qmd, class_id, version_major, version_minor, SHARED_MEMORY_SIZE, \
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align(shader->info.cs.smem_size, 0x100)); \
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} while (0)
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static void
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nva0c0_qmd_init(uint32_t *qmd, const struct nvk_shader *shader)
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{
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nvk_qmd_init_base(qmd, shader, A0C0, 00, 06);
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if (shader->info.cs.smem_size <= (16 << 10))
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NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION, DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB);
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else if (shader->info.cs.smem_size <= (32 << 10))
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NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION, DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB);
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else if (shader->info.cs.smem_size <= (48 << 10))
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NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION, DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB);
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else
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unreachable("Invalid shared memory size");
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uint64_t addr = shader->hdr_addr;
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assert(addr < 0xffffffff);
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NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET, addr);
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NVA0C0_QMDV00_06_VAL_SET(qmd, REGISTER_COUNT, shader->info.num_gprs);
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NVA0C0_QMDV00_06_VAL_SET(qmd, SASS_VERSION, 0x30);
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}
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static void
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nvc0c0_qmd_init(uint32_t *qmd, const struct nvk_shader *shader)
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{
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nvk_qmd_init_base(qmd, shader, C0C0, 02, 01);
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uint64_t addr = shader->hdr_addr;
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assert(addr < 0xffffffff);
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NVC0C0_QMDV02_01_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
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NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET, addr);
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NVC0C0_QMDV02_01_VAL_SET(qmd, REGISTER_COUNT, shader->info.num_gprs);
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}
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static void
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nvc3c0_qmd_init(uint32_t *qmd, const struct nvk_shader *shader)
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{
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nvk_qmd_init_base(qmd, shader, C3C0, 02, 02);
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NVC3C0_QMDV02_02_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
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/* those are all QMD 2.2+ */
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NVC3C0_QMDV02_02_VAL_SET(qmd, MIN_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(shader->info.cs.smem_size));
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NVC3C0_QMDV02_02_VAL_SET(qmd, MAX_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(NVK_MAX_SHARED_SIZE));
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NVC3C0_QMDV02_02_VAL_SET(qmd, TARGET_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(shader->info.cs.smem_size));
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NVC3C0_QMDV02_02_VAL_SET(qmd, REGISTER_COUNT_V, shader->info.num_gprs);
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uint64_t addr = shader->hdr_addr;
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NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, addr & 0xffffffff);
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NVC3C0_QMDV02_02_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, addr >> 32);
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}
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static void
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nvc6c0_qmd_init(uint32_t *qmd, const struct nvk_shader *shader)
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{
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nvk_qmd_init_base(qmd, shader, C6C0, 03, 00);
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NVC6C0_QMDV03_00_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
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/* those are all QMD 2.2+ */
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NVC6C0_QMDV03_00_VAL_SET(qmd, MIN_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(shader->info.cs.smem_size));
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NVC6C0_QMDV03_00_VAL_SET(qmd, MAX_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(NVK_MAX_SHARED_SIZE));
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NVC6C0_QMDV03_00_VAL_SET(qmd, TARGET_SM_CONFIG_SHARED_MEM_SIZE,
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gv100_sm_config_smem_size(shader->info.cs.smem_size));
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NVC6C0_QMDV03_00_VAL_SET(qmd, REGISTER_COUNT_V, shader->info.num_gprs);
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uint64_t addr = shader->hdr_addr;
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NVC6C0_QMDV03_00_VAL_SET(qmd, PROGRAM_ADDRESS_LOWER, addr & 0xffffffff);
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NVC6C0_QMDV03_00_VAL_SET(qmd, PROGRAM_ADDRESS_UPPER, addr >> 32);
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}
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static void
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nvk_qmd_init(struct nvk_physical_device *pdev,
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uint32_t *qmd, const struct nvk_shader *shader)
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{
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if (pdev->info.cls_compute >= AMPERE_COMPUTE_A)
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nvc6c0_qmd_init(qmd, shader);
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else if (pdev->info.cls_compute >= VOLTA_COMPUTE_A)
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nvc3c0_qmd_init(qmd, shader);
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else if (pdev->info.cls_compute >= PASCAL_COMPUTE_A)
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nvc0c0_qmd_init(qmd, shader);
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else if (pdev->info.cls_compute >= KEPLER_COMPUTE_A)
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nva0c0_qmd_init(qmd, shader);
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else
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unreachable("Unknown GPU generation");
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}
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static void
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nva0c0_qmd_set_dispatch_size(UNUSED struct nvk_device *dev, uint32_t *qmd,
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uint32_t x, uint32_t y, uint32_t z)
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{
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NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_WIDTH, x);
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NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_HEIGHT, y);
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NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_DEPTH, z);
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}
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static void
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nvc0c0_qmd_set_dispatch_size(UNUSED struct nvk_device *dev, uint32_t *qmd,
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uint32_t x, uint32_t y, uint32_t z)
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{
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NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_WIDTH, x);
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NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_HEIGHT, y);
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/* this field is different from older QMD versions */
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NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_DEPTH, z);
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}
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static void
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nvc6c0_qmd_set_dispatch_size(UNUSED struct nvk_device *dev, uint32_t *qmd,
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uint32_t x, uint32_t y, uint32_t z)
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{
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NVC6C0_QMDV03_00_VAL_SET(qmd, CTA_RASTER_WIDTH, x);
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NVC6C0_QMDV03_00_VAL_SET(qmd, CTA_RASTER_HEIGHT, y);
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/* this field is different from older QMD versions */
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NVC6C0_QMDV03_00_VAL_SET(qmd, CTA_RASTER_DEPTH, z);
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}
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static uint32_t
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qmd_dispatch_size_offset(const struct nv_device_info *devinfo)
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{
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assert(devinfo->cls_compute >= VOLTA_COMPUTE_A);
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uint32_t bit = DRF_LO(DRF_MW(NVC3C0_QMDV02_02_CTA_RASTER_WIDTH));
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assert(bit % 32 == 0);
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assert(DRF_LO(DRF_MW(NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT)) == bit + 32);
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assert(DRF_LO(DRF_MW(NVC3C0_QMDV02_02_CTA_RASTER_DEPTH)) == bit + 64);
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return bit / 8;
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}
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static inline void
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nva0c0_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index,
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uint32_t size, uint64_t address)
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{
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NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
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NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
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NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_SIZE, index, size);
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NVA0C0_QMDV00_06_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);
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}
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static inline void
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nvc0c0_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index,
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uint32_t size, uint64_t address)
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{
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NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
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NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
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NVC0C0_QMDV02_01_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index,
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DIV_ROUND_UP(size, 16));
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NVC0C0_QMDV02_01_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);
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}
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static inline void
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nvc6c0_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index,
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uint32_t size, uint64_t address)
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{
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NVC6C0_QMDV03_00_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
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NVC6C0_QMDV03_00_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
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NVC6C0_QMDV03_00_VAL_SET(qmd, CONSTANT_BUFFER_SIZE_SHIFTED4, index,
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DIV_ROUND_UP(size, 16));
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NVC6C0_QMDV03_00_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);
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}
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void
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nvk_cmd_bind_compute_shader(struct nvk_cmd_buffer *cmd,
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struct nvk_shader *shader)
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@ -350,28 +134,18 @@ nvk_flush_compute_state(struct nvk_cmd_buffer *cmd,
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desc->root.root_desc_addr = root_desc_addr;
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memcpy(root_desc_map, &desc->root, sizeof(desc->root));
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uint32_t qmd[64];
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memset(qmd, 0, sizeof(qmd));
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nvk_qmd_init(pdev, qmd, shader);
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if (nvk_cmd_buffer_compute_cls(cmd) >= AMPERE_COMPUTE_A) {
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nvc6c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
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desc->root.cs.group_count[0],
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desc->root.cs.group_count[1],
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desc->root.cs.group_count[2]);
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} else if (nvk_cmd_buffer_compute_cls(cmd) >= PASCAL_COMPUTE_A) {
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nvc0c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
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desc->root.cs.group_count[0],
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desc->root.cs.group_count[1],
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desc->root.cs.group_count[2]);
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} else {
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assert(nvk_cmd_buffer_compute_cls(cmd) >= KEPLER_COMPUTE_A);
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nva0c0_qmd_set_dispatch_size(nvk_cmd_buffer_device(cmd), qmd,
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desc->root.cs.group_count[0],
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desc->root.cs.group_count[1],
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desc->root.cs.group_count[2]);
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}
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struct nak_qmd_info qmd_info = {
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.addr = shader->hdr_addr,
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.smem_size = shader->info.cs.smem_size,
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.smem_max = NVK_MAX_SHARED_SIZE,
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.global_size = {
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desc->root.cs.group_count[0],
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desc->root.cs.group_count[1],
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desc->root.cs.group_count[2],
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},
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};
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assert(shader->cbuf_map.cbuf_count <= ARRAY_SIZE(qmd_info.cbufs));
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for (uint32_t c = 0; c < shader->cbuf_map.cbuf_count; c++) {
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const struct nvk_cbuf *cbuf = &shader->cbuf_map.cbufs[c];
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@ -392,17 +166,17 @@ nvk_flush_compute_state(struct nvk_cmd_buffer *cmd,
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ba.size = align(ba.size, min_cbuf_alignment);
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ba.size = MIN2(ba.size, NVK_MAX_CBUF_SIZE);
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if (nvk_cmd_buffer_compute_cls(cmd) >= AMPERE_COMPUTE_A) {
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nvc6c0_cp_launch_desc_set_cb(qmd, c, ba.size, ba.base_addr);
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} else if (nvk_cmd_buffer_compute_cls(cmd) >= PASCAL_COMPUTE_A) {
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nvc0c0_cp_launch_desc_set_cb(qmd, c, ba.size, ba.base_addr);
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} else {
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assert(nvk_cmd_buffer_compute_cls(cmd) >= KEPLER_COMPUTE_A);
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nva0c0_cp_launch_desc_set_cb(qmd, c, ba.size, ba.base_addr);
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}
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qmd_info.cbufs[qmd_info.num_cbufs++] = (struct nak_qmd_cbuf) {
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.index = c,
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.addr = ba.base_addr,
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.size = ba.size,
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};
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}
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}
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uint32_t qmd[64];
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nak_fill_qmd(&pdev->info, &shader->info, &qmd_info, qmd, sizeof(qmd));
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uint64_t qmd_addr;
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result = nvk_cmd_buffer_upload_data(cmd, qmd, sizeof(qmd), 0x100, &qmd_addr);
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if (unlikely(result != VK_SUCCESS)) {
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@ -536,7 +310,7 @@ nvk_mme_dispatch_indirect(struct mme_builder *b)
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mme_tu104_read_fifoed(b, dispatch_addr, mme_imm(3));
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uint32_t qmd_size_offset = qmd_dispatch_size_offset(b->devinfo);
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uint32_t qmd_size_offset = nak_qmd_dispatch_size_offset(b->devinfo);
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uint32_t root_desc_size_offset =
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offsetof(struct nvk_root_descriptor_table, cs.group_count);
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