mirror of https://gitlab.freedesktop.org/mesa/mesa
radv: add a new mechanism for tracking registers per cmdbuf
We already track a couple of registers per cmdbuf and this introduces a generic mechanism, instead of having a bunch of last_xxx fields. Loosely based on RadeonSI. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28644>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
39a9f68685
commit
1173058002
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@ -399,6 +399,16 @@ radv_cmd_buffer_reset_rendering(struct radv_cmd_buffer *cmd_buffer)
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memset(&cmd_buffer->state.render, 0, sizeof(cmd_buffer->state.render));
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}
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static void
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radv_reset_tracked_regs(struct radv_cmd_buffer *cmd_buffer)
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{
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struct radv_tracked_regs *tracked_regs = &cmd_buffer->tracked_regs;
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/* Mark all registers as unknown. */
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memset(tracked_regs->reg_value, 0, RADV_NUM_ALL_TRACKED_REGS * sizeof(uint32_t));
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BITSET_ZERO(tracked_regs->reg_saved_mask);
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}
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static void
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radv_reset_cmd_buffer(struct vk_command_buffer *vk_cmd_buffer, UNUSED VkCommandBufferResetFlags flags)
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{
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@ -1638,12 +1648,8 @@ radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer)
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pa_sc_binner_cntl_0 = radv_get_binning_state(cmd_buffer);
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if (pa_sc_binner_cntl_0 == cmd_buffer->state.last_pa_sc_binner_cntl_0)
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return;
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radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0, pa_sc_binner_cntl_0);
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cmd_buffer->state.last_pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
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radeon_opt_set_context_reg(cmd_buffer, R_028C44_PA_SC_BINNER_CNTL_0, RADV_TRACKED_PA_SC_BINNER_CNTL_0,
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pa_sc_binner_cntl_0);
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}
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static void
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@ -1837,18 +1843,8 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
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* breaks dual source blending in SkQP and does not seem to improve
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* performance. */
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if (sx_ps_downconvert != cmd_buffer->state.last_sx_ps_downconvert ||
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sx_blend_opt_epsilon != cmd_buffer->state.last_sx_blend_opt_epsilon ||
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sx_blend_opt_control != cmd_buffer->state.last_sx_blend_opt_control) {
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
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radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
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radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
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radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
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cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;
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cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;
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cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;
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}
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radeon_opt_set_context_reg3(cmd_buffer, R_028754_SX_PS_DOWNCONVERT, RADV_TRACKED_SX_PS_DOWNCONVERT,
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sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
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cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_RBPLUS;
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}
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@ -2525,10 +2521,8 @@ radv_emit_primitive_restart_enable(struct radv_cmd_buffer *cmd_buffer)
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if (en && gfx_level <= GFX7) {
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const uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer);
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if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
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radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, primitive_reset_index);
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cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
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}
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radeon_opt_set_context_reg(cmd_buffer, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
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RADV_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, primitive_reset_index);
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}
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}
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}
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@ -3879,13 +3873,7 @@ radv_flush_occlusion_query_state(struct radv_cmd_buffer *cmd_buffer)
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}
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}
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if (db_count_control != cmd_buffer->state.last_db_count_control) {
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radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
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cmd_buffer->state.context_roll_without_scissor_emitted = true;
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cmd_buffer->state.last_db_count_control = db_count_control;
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}
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radeon_opt_set_context_reg(cmd_buffer, R_028004_DB_COUNT_CONTROL, RADV_TRACKED_DB_COUNT_CONTROL, db_count_control);
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cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_OCCLUSION_QUERY;
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}
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@ -6073,15 +6061,12 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi
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cmd_buffer->state.last_drawid = -1;
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cmd_buffer->state.last_subpass_color_count = MAX_RTS;
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cmd_buffer->state.predication_type = -1;
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cmd_buffer->state.last_sx_ps_downconvert = -1;
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cmd_buffer->state.last_sx_blend_opt_epsilon = -1;
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cmd_buffer->state.last_sx_blend_opt_control = -1;
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cmd_buffer->state.mesh_shading = false;
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cmd_buffer->state.last_vrs_rates = -1;
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cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;
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cmd_buffer->state.last_pa_sc_binner_cntl_0 = -1;
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cmd_buffer->state.last_db_count_control = -1;
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cmd_buffer->state.last_db_shader_control = -1;
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radv_reset_tracked_regs(cmd_buffer);
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cmd_buffer->usage_flags = pBeginInfo->flags;
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cmd_buffer->state.dirty |=
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@ -8076,10 +8061,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
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primary->state.emitted_compute_pipeline = secondary->state.emitted_compute_pipeline;
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}
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if (secondary->state.last_primitive_reset_index) {
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primary->state.last_primitive_reset_index = secondary->state.last_primitive_reset_index;
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}
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if (secondary->state.last_ia_multi_vgt_param) {
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primary->state.last_ia_multi_vgt_param = secondary->state.last_ia_multi_vgt_param;
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}
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@ -8090,9 +8071,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
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primary->state.last_num_instances = secondary->state.last_num_instances;
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primary->state.last_subpass_color_count = secondary->state.last_subpass_color_count;
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primary->state.last_sx_ps_downconvert = secondary->state.last_sx_ps_downconvert;
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primary->state.last_sx_blend_opt_epsilon = secondary->state.last_sx_blend_opt_epsilon;
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primary->state.last_sx_blend_opt_control = secondary->state.last_sx_blend_opt_control;
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if (secondary->state.last_index_type != -1) {
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primary->state.last_index_type = secondary->state.last_index_type;
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@ -8101,13 +8079,17 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
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primary->state.last_vrs_rates = secondary->state.last_vrs_rates;
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primary->state.last_vrs_rates_sgpr_idx = secondary->state.last_vrs_rates_sgpr_idx;
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primary->state.last_pa_sc_binner_cntl_0 = secondary->state.last_pa_sc_binner_cntl_0;
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primary->state.last_db_shader_control = secondary->state.last_db_shader_control;
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primary->state.rb_noncoherent_dirty |= secondary->state.rb_noncoherent_dirty;
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primary->state.uses_draw_indirect |= secondary->state.uses_draw_indirect;
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for (uint32_t reg = 0; reg < RADV_NUM_ALL_TRACKED_REGS; reg++) {
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if (!BITSET_TEST(secondary->tracked_regs.reg_saved_mask, reg))
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continue;
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BITSET_SET(primary->tracked_regs.reg_saved_mask, reg);
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primary->tracked_regs.reg_value[reg] = secondary->tracked_regs.reg_value[reg];
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}
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}
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/* After executing commands from secondary buffers we have to dirty
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@ -8123,7 +8105,6 @@ radv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCou
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primary->state.last_first_instance = -1;
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primary->state.last_drawid = -1;
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primary->state.last_vertex_offset_valid = false;
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primary->state.last_db_count_control = -1;
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}
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static void
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@ -9445,11 +9426,8 @@ radv_emit_db_shader_control(struct radv_cmd_buffer *cmd_buffer)
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}
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}
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if (db_shader_control != cmd_buffer->state.last_db_shader_control) {
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radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL, db_shader_control);
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cmd_buffer->state.last_db_shader_control = db_shader_control;
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}
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radeon_opt_set_context_reg(cmd_buffer, R_02880C_DB_SHADER_CONTROL, RADV_TRACKED_DB_SHADER_CONTROL,
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db_shader_control);
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cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DB_SHADER_CONTROL;
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}
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@ -290,6 +290,27 @@ enum rgp_flush_bits {
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RGP_FLUSH_INVAL_L1 = 0x8000,
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};
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enum radv_tracked_reg {
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RADV_TRACKED_DB_COUNT_CONTROL,
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RADV_TRACKED_DB_SHADER_CONTROL,
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RADV_TRACKED_PA_SC_BINNER_CNTL_0,
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/* 3 consecutive registers */
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RADV_TRACKED_SX_PS_DOWNCONVERT,
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RADV_TRACKED_SX_BLEND_OPT_EPSILON,
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RADV_TRACKED_SX_BLEND_OPT_CONTROL,
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RADV_TRACKED_VGT_MULTI_PRIM_IB_RESET_INDX, /* GFX6-7 */
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RADV_NUM_ALL_TRACKED_REGS,
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};
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struct radv_tracked_regs {
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BITSET_DECLARE(reg_saved_mask, RADV_NUM_ALL_TRACKED_REGS);
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uint32_t reg_value[RADV_NUM_ALL_TRACKED_REGS];
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};
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struct radv_cmd_state {
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/* Vertex descriptors */
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uint64_t vb_va;
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@ -326,7 +347,6 @@ struct radv_cmd_state {
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uint64_t index_va;
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int32_t last_index_type;
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uint32_t last_primitive_reset_index; /* only relevant on GFX6-7 */
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enum radv_cmd_flush_bits flush_bits;
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unsigned active_occlusion_queries;
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bool perfect_occlusion_queries_enabled;
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@ -348,14 +368,6 @@ struct radv_cmd_state {
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uint32_t last_drawid;
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uint32_t last_subpass_color_count;
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uint32_t last_sx_ps_downconvert;
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uint32_t last_sx_blend_opt_epsilon;
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uint32_t last_sx_blend_opt_control;
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uint32_t last_db_count_control;
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uint32_t last_db_shader_control;
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/* Whether CP DMA is busy/idle. */
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bool dma_is_busy;
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@ -424,9 +436,6 @@ struct radv_cmd_state {
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unsigned spi_shader_col_format;
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unsigned cb_shader_mask;
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/* Binning state */
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unsigned last_pa_sc_binner_cntl_0;
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struct radv_multisample_state ms;
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/* Custom blend mode for internal operations. */
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@ -472,6 +481,8 @@ struct radv_cmd_buffer_upload {
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struct radv_cmd_buffer {
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struct vk_command_buffer vk;
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struct radv_tracked_regs tracked_regs;
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VkCommandBufferUsageFlags usage_flags;
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struct radeon_cmdbuf *cs;
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struct radv_cmd_state state;
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@ -193,6 +193,40 @@ radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigne
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radeon_emit(cs, 0); /* unused */
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}
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#define radeon_opt_set_context_reg(cmdbuf, reg, reg_enum, value) \
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do { \
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struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
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struct radv_tracked_regs *__tracked_regs = &__cmdbuf->tracked_regs; \
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const uint32_t __value = (value); \
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if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
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__tracked_regs->reg_value[(reg_enum)] != __value) { \
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radeon_set_context_reg(__cmdbuf->cs, reg, __value); \
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BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \
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__tracked_regs->reg_value[(reg_enum)] = __value; \
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__cmdbuf->state.context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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#define radeon_opt_set_context_reg3(cmdbuf, reg, reg_enum, v1, v2, v3) \
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do { \
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struct radv_cmd_buffer *__cmdbuf = (cmdbuf); \
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struct radv_tracked_regs *__tracked_regs = &__cmdbuf->tracked_regs; \
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const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2, 0x7) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
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__tracked_regs->reg_value[(reg_enum) + 2] != __v3) { \
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radeon_set_context_reg_seq(cmdbuf->cs, reg, 3); \
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radeon_emit(cmdbuf->cs, __v1); \
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radeon_emit(cmdbuf->cs, __v2); \
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radeon_emit(cmdbuf->cs, __v3); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
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cmdbuf->state.context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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ALWAYS_INLINE static void
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radv_cp_wait_mem(struct radeon_cmdbuf *cs, const enum radv_queue_family qf, const uint32_t op, const uint64_t va,
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const uint32_t ref, const uint32_t mask)
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