2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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2016-10-07 12:19:19 +01:00
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#ifndef RADV_PRIVATE_H
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#define RADV_PRIVATE_H
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2016-10-07 00:16:09 +01:00
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdbool.h>
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#include <pthread.h>
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#include <assert.h>
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#include <stdint.h>
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#include <string.h>
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#ifdef HAVE_VALGRIND
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#include <valgrind.h>
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#include <memcheck.h>
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#define VG(x) x
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#else
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#define VG(x)
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#endif
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#include <amdgpu.h>
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#include "compiler/shader_enums.h"
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#include "util/macros.h"
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#include "util/list.h"
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#include "main/macros.h"
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2017-06-06 12:31:05 +01:00
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#include "vk_alloc.h"
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2016-10-14 04:36:45 +01:00
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2016-10-07 00:16:09 +01:00
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#include "radv_radeon_winsys.h"
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#include "ac_binary.h"
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#include "ac_nir_to_llvm.h"
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2017-05-12 00:11:27 +01:00
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#include "ac_gpu_info.h"
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2017-05-10 22:01:00 +01:00
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#include "ac_surface.h"
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2017-03-05 19:58:31 +00:00
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#include "radv_debug.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_descriptor_set.h"
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#include <llvm-c/TargetMachine.h>
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/* Pre-declarations needed for WSI entrypoints */
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struct wl_surface;
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struct wl_display;
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typedef struct xcb_connection_t xcb_connection_t;
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typedef uint32_t xcb_visualid_t;
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typedef uint32_t xcb_window_t;
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#include <vulkan/vulkan.h>
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#include <vulkan/vulkan_intel.h>
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#include <vulkan/vk_icd.h>
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#include "radv_entrypoints.h"
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2016-10-14 07:49:34 +01:00
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#include "wsi_common.h"
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2016-10-07 00:16:09 +01:00
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#define MAX_VBS 32
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#define MAX_VERTEX_ATTRIBS 32
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#define MAX_RTS 8
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#define MAX_VIEWPORTS 16
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#define MAX_SCISSORS 16
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#define MAX_PUSH_CONSTANTS_SIZE 128
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2017-03-29 17:12:44 +01:00
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#define MAX_PUSH_DESCRIPTORS 32
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2016-10-07 00:16:09 +01:00
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#define MAX_DYNAMIC_BUFFERS 16
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2017-01-11 01:31:24 +00:00
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#define MAX_SAMPLES_LOG2 4
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2016-10-07 00:16:09 +01:00
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#define NUM_META_FS_KEYS 11
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2017-01-16 20:25:10 +00:00
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#define RADV_MAX_DRM_DEVICES 8
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2016-10-07 00:16:09 +01:00
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#define NUM_DEPTH_CLEAR_PIPELINES 3
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2016-12-08 21:28:21 +00:00
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enum radv_mem_heap {
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RADV_MEM_HEAP_VRAM,
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RADV_MEM_HEAP_VRAM_CPU_ACCESS,
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RADV_MEM_HEAP_GTT,
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RADV_MEM_HEAP_COUNT
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};
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2016-12-08 22:06:44 +00:00
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enum radv_mem_type {
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RADV_MEM_TYPE_VRAM,
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RADV_MEM_TYPE_GTT_WRITE_COMBINE,
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RADV_MEM_TYPE_VRAM_CPU_ACCESS,
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RADV_MEM_TYPE_GTT_CACHED,
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RADV_MEM_TYPE_COUNT
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};
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2016-10-07 00:16:09 +01:00
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#define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
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static inline uint32_t
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align_u32(uint32_t v, uint32_t a)
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{
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assert(a != 0 && a == (a & -a));
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return (v + a - 1) & ~(a - 1);
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}
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static inline uint32_t
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align_u32_npot(uint32_t v, uint32_t a)
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{
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return (v + a - 1) / a * a;
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}
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static inline uint64_t
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align_u64(uint64_t v, uint64_t a)
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{
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assert(a != 0 && a == (a & -a));
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return (v + a - 1) & ~(a - 1);
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}
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static inline int32_t
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align_i32(int32_t v, int32_t a)
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{
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assert(a != 0 && a == (a & -a));
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return (v + a - 1) & ~(a - 1);
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}
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/** Alignment must be a power of 2. */
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static inline bool
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radv_is_aligned(uintmax_t n, uintmax_t a)
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{
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assert(a == (a & -a));
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return (n & (a - 1)) == 0;
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}
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static inline uint32_t
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round_up_u32(uint32_t v, uint32_t a)
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{
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return (v + a - 1) / a;
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}
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static inline uint64_t
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round_up_u64(uint64_t v, uint64_t a)
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{
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return (v + a - 1) / a;
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}
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static inline uint32_t
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radv_minify(uint32_t n, uint32_t levels)
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{
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if (unlikely(n == 0))
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return 0;
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else
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2016-10-14 04:11:20 +01:00
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return MAX2(n >> levels, 1);
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2016-10-07 00:16:09 +01:00
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}
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static inline float
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radv_clamp_f(float f, float min, float max)
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{
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assert(min < max);
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if (f > max)
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return max;
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else if (f < min)
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return min;
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else
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return f;
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}
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static inline bool
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radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
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{
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if (*inout_mask & clear_mask) {
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*inout_mask &= ~clear_mask;
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return true;
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} else {
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return false;
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}
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}
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#define for_each_bit(b, dword) \
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for (uint32_t __dword = (dword); \
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(b) = __builtin_ffs(__dword) - 1, __dword; \
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__dword &= ~(1 << (b)))
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#define typed_memcpy(dest, src, count) ({ \
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2016-12-06 23:30:48 +00:00
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STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
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2016-10-07 00:16:09 +01:00
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memcpy((dest), (src), (count) * sizeof(*(src))); \
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})
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#define zero(x) (memset(&(x), 0, sizeof(x)))
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/* Whenever we generate an error, pass it through this function. Useful for
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* debugging, where we can break on it. Only call at error site, not when
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* propagating errors. Might be useful to plug in a stack trace here.
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*/
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VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
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#ifdef DEBUG
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#define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
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#define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
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#else
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#define vk_error(error) error
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#define vk_errorf(error, format, ...) error
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#endif
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void __radv_finishme(const char *file, int line, const char *format, ...)
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radv_printflike(3, 4);
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void radv_loge(const char *format, ...) radv_printflike(1, 2);
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void radv_loge_v(const char *format, va_list va);
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/**
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* Print a FINISHME message, including its source location.
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*/
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#define radv_finishme(format, ...) \
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2016-11-24 18:18:14 +00:00
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do { \
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static bool reported = false; \
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if (!reported) { \
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__radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
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reported = true; \
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} \
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} while (0)
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2016-10-07 00:16:09 +01:00
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/* A non-fatal assert. Useful for debugging. */
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#ifdef DEBUG
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#define radv_assert(x) ({ \
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if (unlikely(!(x))) \
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fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
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})
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#else
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#define radv_assert(x)
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#endif
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#define stub_return(v) \
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do { \
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radv_finishme("stub %s", __func__); \
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return (v); \
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} while (0)
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#define stub() \
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do { \
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radv_finishme("stub %s", __func__); \
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return; \
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} while (0)
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void *radv_lookup_entrypoint(const char *name);
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2017-01-13 23:44:17 +00:00
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struct radv_extensions {
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VkExtensionProperties *ext_array;
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uint32_t num_ext;
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};
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2016-10-07 00:16:09 +01:00
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struct radv_physical_device {
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VK_LOADER_DATA _loader_data;
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struct radv_instance * instance;
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struct radeon_winsys *ws;
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struct radeon_info rad_info;
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char path[20];
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const char * name;
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2016-11-21 23:31:44 +00:00
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uint8_t uuid[VK_UUID_SIZE];
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2017-05-23 08:22:09 +01:00
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uint8_t device_uuid[VK_UUID_SIZE];
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2016-11-21 23:31:44 +00:00
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2017-02-19 05:27:47 +00:00
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int local_fd;
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2016-10-14 07:49:34 +01:00
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struct wsi_device wsi_device;
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2017-01-13 23:44:17 +00:00
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struct radv_extensions extensions;
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2017-06-06 00:03:55 +01:00
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bool has_rbplus; /* if RB+ register exist */
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bool rbplus_allowed; /* if RB+ is allowed */
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2016-10-07 00:16:09 +01:00
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};
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struct radv_instance {
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VK_LOADER_DATA _loader_data;
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VkAllocationCallbacks alloc;
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uint32_t apiVersion;
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int physicalDeviceCount;
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2017-01-16 20:25:10 +00:00
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struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
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2017-01-02 17:57:02 +00:00
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uint64_t debug_flags;
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2017-05-09 04:17:30 +01:00
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uint64_t perftest_flags;
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2016-10-07 00:16:09 +01:00
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};
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VkResult radv_init_wsi(struct radv_physical_device *physical_device);
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void radv_finish_wsi(struct radv_physical_device *physical_device);
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struct cache_entry;
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struct radv_pipeline_cache {
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struct radv_device * device;
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pthread_mutex_t mutex;
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uint32_t total_size;
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uint32_t table_size;
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uint32_t kernel_count;
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struct cache_entry ** hash_table;
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bool modified;
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VkAllocationCallbacks alloc;
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};
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void
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radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
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struct radv_device *device);
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void
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radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
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void
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radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
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const void *data, size_t size);
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struct radv_shader_variant *
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radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
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struct radv_pipeline_cache *cache,
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const unsigned char *sha1);
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struct radv_shader_variant *
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2017-03-20 03:24:02 +00:00
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radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
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2016-10-07 00:16:09 +01:00
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const unsigned char *sha1,
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struct radv_shader_variant *variant,
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const void *code, unsigned code_size);
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void radv_shader_variant_destroy(struct radv_device *device,
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struct radv_shader_variant *variant);
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struct radv_meta_state {
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VkAllocationCallbacks alloc;
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struct radv_pipeline_cache cache;
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/**
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* Use array element `i` for images with `2^i` samples.
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*/
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struct {
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VkRenderPass render_pass[NUM_META_FS_KEYS];
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struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
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2017-01-16 20:37:36 +00:00
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VkRenderPass depthstencil_rp;
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
|
|
|
|
struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
|
|
|
|
struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
|
|
|
|
} clear[1 + MAX_SAMPLES_LOG2];
|
|
|
|
|
2017-04-19 01:34:37 +01:00
|
|
|
VkPipelineLayout clear_color_p_layout;
|
|
|
|
VkPipelineLayout clear_depth_p_layout;
|
2016-10-07 00:16:09 +01:00
|
|
|
struct {
|
|
|
|
VkRenderPass render_pass[NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
/** Pipeline that blits from a 1D image. */
|
|
|
|
VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
/** Pipeline that blits from a 2D image. */
|
|
|
|
VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
/** Pipeline that blits from a 3D image. */
|
|
|
|
VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
VkRenderPass depth_only_rp;
|
|
|
|
VkPipeline depth_only_1d_pipeline;
|
|
|
|
VkPipeline depth_only_2d_pipeline;
|
|
|
|
VkPipeline depth_only_3d_pipeline;
|
|
|
|
|
|
|
|
VkRenderPass stencil_only_rp;
|
|
|
|
VkPipeline stencil_only_1d_pipeline;
|
|
|
|
VkPipeline stencil_only_2d_pipeline;
|
|
|
|
VkPipeline stencil_only_3d_pipeline;
|
|
|
|
VkPipelineLayout pipeline_layout;
|
|
|
|
VkDescriptorSetLayout ds_layout;
|
|
|
|
} blit;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
VkRenderPass render_passes[NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
VkPipelineLayout p_layouts[2];
|
|
|
|
VkDescriptorSetLayout ds_layouts[2];
|
|
|
|
VkPipeline pipelines[2][NUM_META_FS_KEYS];
|
|
|
|
|
|
|
|
VkRenderPass depth_only_rp;
|
|
|
|
VkPipeline depth_only_pipeline[2];
|
|
|
|
|
|
|
|
VkRenderPass stencil_only_rp;
|
|
|
|
VkPipeline stencil_only_pipeline[2];
|
|
|
|
} blit2d;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
VkPipelineLayout img_p_layout;
|
|
|
|
VkDescriptorSetLayout img_ds_layout;
|
|
|
|
VkPipeline pipeline;
|
|
|
|
} itob;
|
|
|
|
struct {
|
|
|
|
VkRenderPass render_pass;
|
|
|
|
VkPipelineLayout img_p_layout;
|
|
|
|
VkDescriptorSetLayout img_ds_layout;
|
|
|
|
VkPipeline pipeline;
|
|
|
|
} btoi;
|
2016-11-30 00:26:47 +00:00
|
|
|
struct {
|
|
|
|
VkPipelineLayout img_p_layout;
|
|
|
|
VkDescriptorSetLayout img_ds_layout;
|
|
|
|
VkPipeline pipeline;
|
|
|
|
} itoi;
|
2016-11-30 01:45:24 +00:00
|
|
|
struct {
|
|
|
|
VkPipelineLayout img_p_layout;
|
|
|
|
VkDescriptorSetLayout img_ds_layout;
|
|
|
|
VkPipeline pipeline;
|
|
|
|
} cleari;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
struct {
|
|
|
|
VkPipeline pipeline;
|
|
|
|
VkRenderPass pass;
|
|
|
|
} resolve;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
VkDescriptorSetLayout ds_layout;
|
|
|
|
VkPipelineLayout p_layout;
|
|
|
|
struct {
|
|
|
|
VkPipeline pipeline;
|
|
|
|
VkPipeline i_pipeline;
|
2017-04-20 04:42:26 +01:00
|
|
|
VkPipeline srgb_pipeline;
|
2016-10-07 00:16:09 +01:00
|
|
|
} rc[MAX_SAMPLES_LOG2];
|
|
|
|
} resolve_compute;
|
|
|
|
|
2017-04-27 01:47:22 +01:00
|
|
|
struct {
|
|
|
|
VkDescriptorSetLayout ds_layout;
|
|
|
|
VkPipelineLayout p_layout;
|
|
|
|
|
|
|
|
struct {
|
2017-05-11 01:05:58 +01:00
|
|
|
VkRenderPass srgb_render_pass;
|
|
|
|
VkPipeline srgb_pipeline;
|
2017-04-27 01:47:22 +01:00
|
|
|
VkRenderPass render_pass[NUM_META_FS_KEYS];
|
|
|
|
VkPipeline pipeline[NUM_META_FS_KEYS];
|
|
|
|
} rc[MAX_SAMPLES_LOG2];
|
|
|
|
} resolve_fragment;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct {
|
|
|
|
VkPipeline decompress_pipeline;
|
|
|
|
VkPipeline resummarize_pipeline;
|
|
|
|
VkRenderPass pass;
|
|
|
|
} depth_decomp;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
VkPipeline cmask_eliminate_pipeline;
|
|
|
|
VkPipeline fmask_decompress_pipeline;
|
|
|
|
VkRenderPass pass;
|
|
|
|
} fast_clear_flush;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
VkPipelineLayout fill_p_layout;
|
|
|
|
VkPipelineLayout copy_p_layout;
|
|
|
|
VkDescriptorSetLayout fill_ds_layout;
|
|
|
|
VkDescriptorSetLayout copy_ds_layout;
|
|
|
|
VkPipeline fill_pipeline;
|
|
|
|
VkPipeline copy_pipeline;
|
|
|
|
} buffer;
|
2017-02-26 17:21:01 +00:00
|
|
|
|
|
|
|
struct {
|
2017-04-10 20:49:48 +01:00
|
|
|
VkDescriptorSetLayout ds_layout;
|
|
|
|
VkPipelineLayout p_layout;
|
2017-02-26 17:21:01 +00:00
|
|
|
VkPipeline occlusion_query_pipeline;
|
2017-04-10 21:20:19 +01:00
|
|
|
VkPipeline pipeline_statistics_query_pipeline;
|
2017-02-26 17:21:01 +00:00
|
|
|
} query;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2016-11-30 04:30:06 +00:00
|
|
|
/* queue types */
|
|
|
|
#define RADV_QUEUE_GENERAL 0
|
|
|
|
#define RADV_QUEUE_COMPUTE 1
|
|
|
|
#define RADV_QUEUE_TRANSFER 2
|
|
|
|
|
|
|
|
#define RADV_MAX_QUEUE_FAMILIES 3
|
|
|
|
|
2016-12-01 00:05:29 +00:00
|
|
|
enum ring_type radv_queue_family_to_ring(int f);
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_queue {
|
|
|
|
VK_LOADER_DATA _loader_data;
|
|
|
|
struct radv_device * device;
|
2017-01-13 23:44:15 +00:00
|
|
|
struct radeon_winsys_ctx *hw_ctx;
|
2016-11-30 04:30:06 +00:00
|
|
|
int queue_family_index;
|
|
|
|
int queue_idx;
|
2017-01-29 12:53:05 +00:00
|
|
|
|
|
|
|
uint32_t scratch_size;
|
|
|
|
uint32_t compute_scratch_size;
|
2017-01-20 01:06:52 +00:00
|
|
|
uint32_t esgs_ring_size;
|
|
|
|
uint32_t gsvs_ring_size;
|
2017-03-30 08:02:14 +01:00
|
|
|
bool has_tess_rings;
|
2017-04-03 04:38:12 +01:00
|
|
|
bool has_sample_positions;
|
2017-01-29 12:53:05 +00:00
|
|
|
|
|
|
|
struct radeon_winsys_bo *scratch_bo;
|
|
|
|
struct radeon_winsys_bo *descriptor_bo;
|
|
|
|
struct radeon_winsys_bo *compute_scratch_bo;
|
2017-01-20 01:06:52 +00:00
|
|
|
struct radeon_winsys_bo *esgs_ring_bo;
|
|
|
|
struct radeon_winsys_bo *gsvs_ring_bo;
|
2017-03-30 08:02:14 +01:00
|
|
|
struct radeon_winsys_bo *tess_factor_ring_bo;
|
|
|
|
struct radeon_winsys_bo *tess_offchip_ring_bo;
|
2017-02-20 08:26:00 +00:00
|
|
|
struct radeon_winsys_cs *initial_preamble_cs;
|
|
|
|
struct radeon_winsys_cs *continue_preamble_cs;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_device {
|
|
|
|
VK_LOADER_DATA _loader_data;
|
|
|
|
|
|
|
|
VkAllocationCallbacks alloc;
|
|
|
|
|
|
|
|
struct radv_instance * instance;
|
|
|
|
struct radeon_winsys *ws;
|
|
|
|
|
|
|
|
struct radv_meta_state meta_state;
|
2016-11-30 04:30:06 +00:00
|
|
|
|
|
|
|
struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
|
|
|
|
int queue_count[RADV_MAX_QUEUE_FAMILIES];
|
2016-12-17 20:53:38 +00:00
|
|
|
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
|
2017-02-20 08:26:00 +00:00
|
|
|
struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
|
2017-05-02 22:13:21 +01:00
|
|
|
struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
|
2017-01-02 17:57:02 +00:00
|
|
|
uint64_t debug_flags;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2017-01-29 14:20:03 +00:00
|
|
|
bool llvm_supports_spill;
|
2017-03-30 07:58:22 +01:00
|
|
|
bool has_distributed_tess;
|
|
|
|
uint32_t tess_offchip_block_dw_size;
|
2017-01-29 14:20:03 +00:00
|
|
|
uint32_t scratch_waves;
|
2017-01-18 03:54:17 +00:00
|
|
|
|
|
|
|
uint32_t gs_table_depth;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
/* MSAA sample locations.
|
|
|
|
* The first index is the sample index.
|
|
|
|
* The second index is the coordinate: X, Y. */
|
|
|
|
float sample_locations_1x[1][2];
|
|
|
|
float sample_locations_2x[2][2];
|
|
|
|
float sample_locations_4x[4][2];
|
|
|
|
float sample_locations_8x[8][2];
|
|
|
|
float sample_locations_16x[16][2];
|
2016-12-23 22:51:18 +00:00
|
|
|
|
2017-02-13 04:00:24 +00:00
|
|
|
/* CIK and later */
|
|
|
|
uint32_t gfx_init_size_dw;
|
|
|
|
struct radeon_winsys_bo *gfx_init;
|
|
|
|
|
2016-12-23 22:51:18 +00:00
|
|
|
struct radeon_winsys_bo *trace_bo;
|
|
|
|
uint32_t *trace_id_ptr;
|
2017-01-16 20:23:48 +00:00
|
|
|
|
|
|
|
struct radv_physical_device *physical_device;
|
2017-03-15 03:14:24 +00:00
|
|
|
|
|
|
|
/* Backup in-memory cache to be used if the app doesn't provide one */
|
|
|
|
struct radv_pipeline_cache * mem_cache;
|
2017-07-07 06:56:57 +01:00
|
|
|
|
|
|
|
uint32_t image_mrt_offset_counter;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_device_memory {
|
|
|
|
struct radeon_winsys_bo *bo;
|
2017-02-26 23:52:08 +00:00
|
|
|
/* for dedicated allocations */
|
|
|
|
struct radv_image *image;
|
|
|
|
struct radv_buffer *buffer;
|
2016-10-07 00:16:09 +01:00
|
|
|
uint32_t type_index;
|
|
|
|
VkDeviceSize map_size;
|
|
|
|
void * map;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
struct radv_descriptor_range {
|
|
|
|
uint64_t va;
|
|
|
|
uint32_t size;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_descriptor_set {
|
|
|
|
const struct radv_descriptor_set_layout *layout;
|
|
|
|
uint32_t size;
|
|
|
|
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
uint64_t va;
|
|
|
|
uint32_t *mapped_ptr;
|
|
|
|
struct radv_descriptor_range *dynamic_descriptors;
|
|
|
|
|
2017-02-16 20:23:58 +00:00
|
|
|
struct list_head vram_list;
|
|
|
|
|
|
|
|
struct radeon_winsys_bo *descriptors[0];
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2017-03-29 17:12:44 +01:00
|
|
|
struct radv_push_descriptor_set
|
|
|
|
{
|
|
|
|
struct radv_descriptor_set set;
|
|
|
|
uint32_t capacity;
|
|
|
|
};
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_descriptor_pool {
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
uint8_t *mapped_ptr;
|
|
|
|
uint64_t current_offset;
|
|
|
|
uint64_t size;
|
|
|
|
|
2017-02-16 20:23:58 +00:00
|
|
|
struct list_head vram_list;
|
2017-04-17 01:14:06 +01:00
|
|
|
|
|
|
|
uint8_t *host_memory_base;
|
|
|
|
uint8_t *host_memory_ptr;
|
|
|
|
uint8_t *host_memory_end;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2017-03-29 18:19:47 +01:00
|
|
|
struct radv_descriptor_update_template_entry {
|
|
|
|
VkDescriptorType descriptor_type;
|
|
|
|
|
|
|
|
/* The number of descriptors to update */
|
2017-04-13 22:49:00 +01:00
|
|
|
uint32_t descriptor_count;
|
2017-03-29 18:19:47 +01:00
|
|
|
|
|
|
|
/* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
|
2017-04-13 22:49:00 +01:00
|
|
|
uint32_t dst_offset;
|
2017-03-29 18:19:47 +01:00
|
|
|
|
|
|
|
/* In dwords. Not valid/used for dynamic descriptors */
|
2017-04-13 22:49:00 +01:00
|
|
|
uint32_t dst_stride;
|
2017-03-29 18:19:47 +01:00
|
|
|
|
2017-04-13 22:49:00 +01:00
|
|
|
uint32_t buffer_offset;
|
2017-03-29 18:19:47 +01:00
|
|
|
|
|
|
|
/* Only valid for combined image samplers and samplers */
|
|
|
|
uint16_t has_sampler;
|
|
|
|
|
|
|
|
/* In bytes */
|
|
|
|
size_t src_offset;
|
|
|
|
size_t src_stride;
|
|
|
|
|
|
|
|
/* For push descriptors */
|
2017-04-11 23:37:06 +01:00
|
|
|
const uint32_t *immutable_samplers;
|
2017-03-29 18:19:47 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_descriptor_update_template {
|
|
|
|
uint32_t entry_count;
|
|
|
|
struct radv_descriptor_update_template_entry entry[0];
|
|
|
|
};
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_buffer {
|
|
|
|
struct radv_device * device;
|
|
|
|
VkDeviceSize size;
|
|
|
|
|
|
|
|
VkBufferUsageFlags usage;
|
2017-02-04 10:15:59 +00:00
|
|
|
VkBufferCreateFlags flags;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
/* Set when bound */
|
|
|
|
struct radeon_winsys_bo * bo;
|
|
|
|
VkDeviceSize offset;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
enum radv_cmd_dirty_bits {
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
|
|
|
|
RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
|
|
|
|
RADV_CMD_DIRTY_PIPELINE = 1 << 9,
|
|
|
|
RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
|
|
|
|
RADV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
|
|
|
|
};
|
|
|
|
typedef uint32_t radv_cmd_dirty_mask_t;
|
|
|
|
|
|
|
|
enum radv_cmd_flush_bits {
|
|
|
|
RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
|
|
|
|
/* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
|
|
|
|
RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
|
|
|
|
/* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
|
|
|
|
RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
|
|
|
|
/* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
|
|
|
|
RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
|
2017-03-06 00:28:53 +00:00
|
|
|
/* Same as above, but only writes back and doesn't invalidate */
|
|
|
|
RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
|
2016-10-07 00:16:09 +01:00
|
|
|
/* Framebuffer caches */
|
2017-03-06 00:28:53 +00:00
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
|
2016-10-07 00:16:09 +01:00
|
|
|
/* Engine synchronization. */
|
2017-03-06 00:28:53 +00:00
|
|
|
RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
|
|
|
|
RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
|
|
|
|
RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
|
|
|
|
RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB |
|
|
|
|
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_vertex_binding {
|
|
|
|
struct radv_buffer * buffer;
|
|
|
|
VkDeviceSize offset;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_dynamic_state {
|
|
|
|
struct {
|
|
|
|
uint32_t count;
|
|
|
|
VkViewport viewports[MAX_VIEWPORTS];
|
|
|
|
} viewport;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
uint32_t count;
|
|
|
|
VkRect2D scissors[MAX_SCISSORS];
|
|
|
|
} scissor;
|
|
|
|
|
|
|
|
float line_width;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
float bias;
|
|
|
|
float clamp;
|
|
|
|
float slope;
|
|
|
|
} depth_bias;
|
|
|
|
|
|
|
|
float blend_constants[4];
|
|
|
|
|
|
|
|
struct {
|
|
|
|
float min;
|
|
|
|
float max;
|
|
|
|
} depth_bounds;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
uint32_t front;
|
|
|
|
uint32_t back;
|
|
|
|
} stencil_compare_mask;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
uint32_t front;
|
|
|
|
uint32_t back;
|
|
|
|
} stencil_write_mask;
|
|
|
|
|
|
|
|
struct {
|
|
|
|
uint32_t front;
|
|
|
|
uint32_t back;
|
|
|
|
} stencil_reference;
|
|
|
|
};
|
|
|
|
|
|
|
|
extern const struct radv_dynamic_state default_dynamic_state;
|
|
|
|
|
|
|
|
void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
|
|
|
|
const struct radv_dynamic_state *src,
|
|
|
|
uint32_t copy_mask);
|
|
|
|
/**
|
|
|
|
* Attachment state when recording a renderpass instance.
|
|
|
|
*
|
|
|
|
* The clear value is valid only if there exists a pending clear.
|
|
|
|
*/
|
|
|
|
struct radv_attachment_state {
|
|
|
|
VkImageAspectFlags pending_clear_aspects;
|
|
|
|
VkClearValue clear_value;
|
|
|
|
VkImageLayout current_layout;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_cmd_state {
|
|
|
|
uint32_t vb_dirty;
|
|
|
|
radv_cmd_dirty_mask_t dirty;
|
2017-03-29 17:12:44 +01:00
|
|
|
bool push_descriptors_dirty;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
struct radv_pipeline * pipeline;
|
|
|
|
struct radv_pipeline * emitted_pipeline;
|
|
|
|
struct radv_pipeline * compute_pipeline;
|
|
|
|
struct radv_pipeline * emitted_compute_pipeline;
|
|
|
|
struct radv_framebuffer * framebuffer;
|
|
|
|
struct radv_render_pass * pass;
|
|
|
|
const struct radv_subpass * subpass;
|
|
|
|
struct radv_dynamic_state dynamic;
|
|
|
|
struct radv_vertex_binding vertex_bindings[MAX_VBS];
|
|
|
|
struct radv_descriptor_set * descriptors[MAX_SETS];
|
|
|
|
struct radv_attachment_state * attachments;
|
|
|
|
VkRect2D render_area;
|
|
|
|
uint32_t index_type;
|
2017-06-07 00:14:54 +01:00
|
|
|
uint64_t index_va;
|
|
|
|
uint32_t max_index_count;
|
2017-04-12 09:20:42 +01:00
|
|
|
int32_t last_primitive_reset_en;
|
2016-10-07 00:16:09 +01:00
|
|
|
uint32_t last_primitive_reset_index;
|
|
|
|
enum radv_cmd_flush_bits flush_bits;
|
|
|
|
unsigned active_occlusion_queries;
|
|
|
|
float offset_scale;
|
2016-11-28 00:42:56 +00:00
|
|
|
uint32_t descriptors_dirty;
|
2016-12-23 22:51:18 +00:00
|
|
|
uint32_t trace_id;
|
2017-02-13 07:30:29 +00:00
|
|
|
uint32_t last_ia_multi_vgt_param;
|
2017-06-26 02:13:24 +01:00
|
|
|
bool predicating;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
2016-12-01 00:05:29 +00:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_cmd_pool {
|
|
|
|
VkAllocationCallbacks alloc;
|
|
|
|
struct list_head cmd_buffers;
|
2017-03-05 21:25:20 +00:00
|
|
|
struct list_head free_cmd_buffers;
|
2016-12-01 00:05:29 +00:00
|
|
|
uint32_t queue_family_index;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_cmd_buffer_upload {
|
|
|
|
uint8_t *map;
|
|
|
|
unsigned offset;
|
|
|
|
uint64_t size;
|
|
|
|
struct radeon_winsys_bo *upload_bo;
|
|
|
|
struct list_head list;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_cmd_buffer {
|
|
|
|
VK_LOADER_DATA _loader_data;
|
|
|
|
|
|
|
|
struct radv_device * device;
|
|
|
|
|
|
|
|
struct radv_cmd_pool * pool;
|
|
|
|
struct list_head pool_link;
|
|
|
|
|
|
|
|
VkCommandBufferUsageFlags usage_flags;
|
|
|
|
VkCommandBufferLevel level;
|
|
|
|
struct radeon_winsys_cs *cs;
|
|
|
|
struct radv_cmd_state state;
|
2016-12-01 00:05:29 +00:00
|
|
|
uint32_t queue_family_index;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
|
2017-03-07 00:53:21 +00:00
|
|
|
uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
|
2016-10-07 00:16:09 +01:00
|
|
|
VkShaderStageFlags push_constant_stages;
|
2017-03-29 17:12:44 +01:00
|
|
|
struct radv_push_descriptor_set push_descriptors;
|
2017-04-13 23:26:58 +01:00
|
|
|
struct radv_descriptor_set meta_push_descriptors;
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
struct radv_cmd_buffer_upload upload;
|
|
|
|
|
2017-01-29 14:20:03 +00:00
|
|
|
uint32_t scratch_size_needed;
|
|
|
|
uint32_t compute_scratch_size_needed;
|
2017-01-20 01:06:52 +00:00
|
|
|
uint32_t esgs_ring_size_needed;
|
|
|
|
uint32_t gsvs_ring_size_needed;
|
2017-03-30 08:02:14 +01:00
|
|
|
bool tess_rings_needed;
|
2017-04-03 04:38:12 +01:00
|
|
|
bool sample_positions_needed;
|
2017-01-20 01:06:52 +00:00
|
|
|
|
2017-05-02 01:32:02 +01:00
|
|
|
bool record_fail;
|
|
|
|
|
2017-01-20 01:06:52 +00:00
|
|
|
int ring_offsets_idx; /* just used for verification */
|
2017-06-06 00:01:48 +01:00
|
|
|
uint32_t gfx9_fence_offset;
|
|
|
|
struct radeon_winsys_bo *gfx9_fence_bo;
|
|
|
|
uint32_t gfx9_fence_idx;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_image;
|
|
|
|
|
2016-12-01 00:05:29 +00:00
|
|
|
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
|
2017-02-13 03:35:37 +00:00
|
|
|
void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
void si_init_config(struct radv_cmd_buffer *cmd_buffer);
|
2017-02-13 04:00:24 +00:00
|
|
|
|
|
|
|
void cik_create_gfx_config(struct radv_device *device);
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
|
|
|
|
int count, const VkViewport *viewports);
|
|
|
|
void si_write_scissors(struct radeon_winsys_cs *cs, int first,
|
2017-03-01 08:32:19 +00:00
|
|
|
int count, const VkRect2D *scissors,
|
|
|
|
const VkViewport *viewports, bool can_use_guardband);
|
2017-02-13 07:30:29 +00:00
|
|
|
uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
|
2017-03-27 20:53:50 +01:00
|
|
|
bool instanced_draw, bool indirect_draw,
|
|
|
|
uint32_t draw_vertex_count);
|
2017-06-01 05:24:34 +01:00
|
|
|
void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
|
2017-06-26 02:13:24 +01:00
|
|
|
bool predicated,
|
2017-06-01 05:24:34 +01:00
|
|
|
enum chip_class chip_class,
|
|
|
|
bool is_mec,
|
|
|
|
unsigned event, unsigned event_flags,
|
|
|
|
unsigned data_sel,
|
|
|
|
uint64_t va,
|
|
|
|
uint32_t old_fence,
|
|
|
|
uint32_t new_fence);
|
|
|
|
|
2017-06-01 05:12:19 +01:00
|
|
|
void si_emit_wait_fence(struct radeon_winsys_cs *cs,
|
2017-06-26 02:13:24 +01:00
|
|
|
bool predicated,
|
2017-06-01 05:12:19 +01:00
|
|
|
uint64_t va, uint32_t ref,
|
|
|
|
uint32_t mask);
|
2017-02-20 08:26:00 +00:00
|
|
|
void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
|
2017-06-26 02:13:24 +01:00
|
|
|
bool predicated,
|
2017-06-06 00:01:48 +01:00
|
|
|
enum chip_class chip_class,
|
|
|
|
uint32_t *fence_ptr, uint64_t va,
|
|
|
|
bool is_mec,
|
|
|
|
enum radv_cmd_flush_bits flush_bits);
|
2016-10-07 00:16:09 +01:00
|
|
|
void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
|
2017-03-02 21:39:10 +00:00
|
|
|
void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
|
2016-10-07 00:16:09 +01:00
|
|
|
void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
uint64_t src_va, uint64_t dest_va,
|
|
|
|
uint64_t size);
|
2017-04-19 21:32:16 +01:00
|
|
|
void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
|
|
|
|
unsigned size);
|
2016-10-07 00:16:09 +01:00
|
|
|
void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
|
|
|
|
uint64_t size, unsigned value);
|
|
|
|
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_descriptor_set *set,
|
|
|
|
unsigned idx);
|
|
|
|
bool
|
|
|
|
radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
unsigned size,
|
|
|
|
unsigned alignment,
|
|
|
|
unsigned *out_offset,
|
|
|
|
void **ptr);
|
|
|
|
void
|
|
|
|
radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
const struct radv_subpass *subpass,
|
|
|
|
bool transitions);
|
|
|
|
bool
|
|
|
|
radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
unsigned size, unsigned alignmnet,
|
|
|
|
const void *data, unsigned *out_offset);
|
|
|
|
void
|
|
|
|
radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
|
2017-05-04 04:02:08 +01:00
|
|
|
void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
|
2017-04-27 01:47:22 +01:00
|
|
|
void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
|
2016-10-07 00:16:09 +01:00
|
|
|
void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
|
|
|
|
unsigned radv_cayman_get_maxdist(int log_samples);
|
|
|
|
void radv_device_init_msaa(struct radv_device *device);
|
|
|
|
void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *image,
|
|
|
|
VkClearDepthStencilValue ds_clear_value,
|
|
|
|
VkImageAspectFlags aspects);
|
|
|
|
void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *image,
|
|
|
|
int idx,
|
|
|
|
uint32_t color_values[2]);
|
2017-03-02 21:39:10 +00:00
|
|
|
void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *image,
|
|
|
|
bool value);
|
2016-10-07 00:16:09 +01:00
|
|
|
void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radeon_winsys_bo *bo,
|
|
|
|
uint64_t offset, uint64_t size, uint32_t value);
|
2016-12-23 22:51:18 +00:00
|
|
|
void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
|
2017-02-26 23:52:08 +00:00
|
|
|
bool radv_get_memory_fd(struct radv_device *device,
|
|
|
|
struct radv_device_memory *memory,
|
|
|
|
int *pFD);
|
2016-10-07 00:16:09 +01:00
|
|
|
/*
|
|
|
|
* Takes x,y,z as exact numbers of invocations, instead of blocks.
|
|
|
|
*
|
|
|
|
* Limitations: Can't call normal dispatch functions without binding or rebinding
|
|
|
|
* the compute pipeline.
|
|
|
|
*/
|
|
|
|
void radv_unaligned_dispatch(
|
|
|
|
struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
uint32_t x,
|
|
|
|
uint32_t y,
|
|
|
|
uint32_t z);
|
|
|
|
|
|
|
|
struct radv_event {
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
uint64_t *map;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct nir_shader;
|
|
|
|
|
|
|
|
struct radv_shader_module {
|
|
|
|
struct nir_shader * nir;
|
|
|
|
unsigned char sha1[20];
|
|
|
|
uint32_t size;
|
|
|
|
char data[0];
|
|
|
|
};
|
|
|
|
|
|
|
|
union ac_shader_variant_key;
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
|
|
|
|
const char *entrypoint,
|
|
|
|
const VkSpecializationInfo *spec_info,
|
|
|
|
const struct radv_pipeline_layout *layout,
|
2017-01-19 23:55:37 +00:00
|
|
|
const union ac_shader_variant_key *key,
|
|
|
|
uint32_t is_geom_copy_shader);
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
static inline gl_shader_stage
|
|
|
|
vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
|
|
|
|
{
|
|
|
|
assert(__builtin_popcount(vk_stage) == 1);
|
|
|
|
return ffs(vk_stage) - 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline VkShaderStageFlagBits
|
|
|
|
mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
|
|
|
|
{
|
|
|
|
return (1 << mesa_stage);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
|
|
|
|
|
|
|
|
#define radv_foreach_stage(stage, stage_bits) \
|
|
|
|
for (gl_shader_stage stage, \
|
|
|
|
__tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
|
|
|
|
stage = __builtin_ffs(__tmp) - 1, __tmp; \
|
|
|
|
__tmp &= ~(1 << (stage)))
|
|
|
|
|
|
|
|
struct radv_shader_variant {
|
|
|
|
uint32_t ref_count;
|
|
|
|
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
struct ac_shader_config config;
|
|
|
|
struct ac_shader_variant_info info;
|
|
|
|
unsigned rsrc1;
|
|
|
|
unsigned rsrc2;
|
2016-11-22 04:17:49 +00:00
|
|
|
uint32_t code_size;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_depth_stencil_state {
|
|
|
|
uint32_t db_depth_control;
|
|
|
|
uint32_t db_stencil_control;
|
|
|
|
uint32_t db_render_control;
|
|
|
|
uint32_t db_render_override2;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_blend_state {
|
|
|
|
uint32_t cb_color_control;
|
|
|
|
uint32_t cb_target_mask;
|
|
|
|
uint32_t sx_mrt0_blend_opt[8];
|
|
|
|
uint32_t cb_blend_control[8];
|
|
|
|
|
|
|
|
uint32_t spi_shader_col_format;
|
|
|
|
uint32_t cb_shader_mask;
|
|
|
|
uint32_t db_alpha_to_mask;
|
|
|
|
};
|
|
|
|
|
|
|
|
unsigned radv_format_meta_fs_key(VkFormat format);
|
|
|
|
|
|
|
|
struct radv_raster_state {
|
|
|
|
uint32_t pa_cl_clip_cntl;
|
|
|
|
uint32_t spi_interp_control;
|
|
|
|
uint32_t pa_su_point_size;
|
|
|
|
uint32_t pa_su_point_minmax;
|
|
|
|
uint32_t pa_su_line_cntl;
|
|
|
|
uint32_t pa_su_vtx_cntl;
|
|
|
|
uint32_t pa_su_sc_mode_cntl;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_multisample_state {
|
|
|
|
uint32_t db_eqaa;
|
|
|
|
uint32_t pa_sc_line_cntl;
|
|
|
|
uint32_t pa_sc_mode_cntl_0;
|
|
|
|
uint32_t pa_sc_mode_cntl_1;
|
|
|
|
uint32_t pa_sc_aa_config;
|
|
|
|
uint32_t pa_sc_aa_mask[2];
|
|
|
|
unsigned num_samples;
|
|
|
|
};
|
|
|
|
|
2017-02-13 07:30:29 +00:00
|
|
|
struct radv_prim_vertex_count {
|
|
|
|
uint8_t min;
|
|
|
|
uint8_t incr;
|
|
|
|
};
|
|
|
|
|
2017-03-30 08:18:13 +01:00
|
|
|
struct radv_tessellation_state {
|
|
|
|
uint32_t ls_hs_config;
|
|
|
|
uint32_t tcs_in_layout;
|
|
|
|
uint32_t tcs_out_layout;
|
|
|
|
uint32_t tcs_out_offsets;
|
|
|
|
uint32_t offchip_layout;
|
|
|
|
unsigned num_patches;
|
|
|
|
unsigned lds_size;
|
|
|
|
unsigned num_tcs_input_cp;
|
|
|
|
uint32_t tf_param;
|
|
|
|
};
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_pipeline {
|
|
|
|
struct radv_device * device;
|
|
|
|
uint32_t dynamic_state_mask;
|
|
|
|
struct radv_dynamic_state dynamic_state;
|
|
|
|
|
|
|
|
struct radv_pipeline_layout * layout;
|
|
|
|
|
|
|
|
bool needs_data_cache;
|
2017-04-18 01:21:59 +01:00
|
|
|
bool need_indirect_descriptor_sets;
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
|
2017-01-19 23:55:37 +00:00
|
|
|
struct radv_shader_variant *gs_copy_shader;
|
2016-10-07 00:16:09 +01:00
|
|
|
VkShaderStageFlags active_stages;
|
|
|
|
|
|
|
|
uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t va_binding[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t va_offset[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t num_vertex_attribs;
|
|
|
|
uint32_t binding_stride[MAX_VBS];
|
|
|
|
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
struct radv_blend_state blend;
|
|
|
|
struct radv_depth_stencil_state ds;
|
|
|
|
struct radv_raster_state raster;
|
|
|
|
struct radv_multisample_state ms;
|
2017-03-30 08:18:13 +01:00
|
|
|
struct radv_tessellation_state tess;
|
2017-03-28 02:34:19 +01:00
|
|
|
uint32_t db_shader_control;
|
2017-03-28 02:34:46 +01:00
|
|
|
uint32_t shader_z_format;
|
2016-10-07 00:16:09 +01:00
|
|
|
unsigned prim;
|
|
|
|
unsigned gs_out;
|
2017-03-28 02:33:35 +01:00
|
|
|
uint32_t vgt_gs_mode;
|
2017-06-20 04:21:04 +01:00
|
|
|
bool vgt_primitiveid_en;
|
2016-10-07 00:16:09 +01:00
|
|
|
bool prim_restart_enable;
|
2017-01-20 00:21:19 +00:00
|
|
|
unsigned esgs_ring_size;
|
|
|
|
unsigned gsvs_ring_size;
|
2017-03-28 02:43:48 +01:00
|
|
|
uint32_t ps_input_cntl[32];
|
|
|
|
uint32_t ps_input_cntl_num;
|
2017-03-28 02:48:38 +01:00
|
|
|
uint32_t pa_cl_vs_out_cntl;
|
2017-03-28 03:59:17 +01:00
|
|
|
uint32_t vgt_shader_stages_en;
|
2017-06-07 00:04:30 +01:00
|
|
|
uint32_t vtx_base_sgpr;
|
|
|
|
uint8_t vtx_emit_num;
|
2017-02-13 07:30:29 +00:00
|
|
|
struct radv_prim_vertex_count prim_vertex_count;
|
2017-03-29 21:58:10 +01:00
|
|
|
bool can_use_guardband;
|
2016-10-07 00:16:09 +01:00
|
|
|
} graphics;
|
|
|
|
};
|
2017-01-29 14:20:03 +00:00
|
|
|
|
|
|
|
unsigned max_waves;
|
|
|
|
unsigned scratch_bytes_per_wave;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2017-01-18 03:50:16 +00:00
|
|
|
static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
|
|
|
|
{
|
|
|
|
return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
|
|
|
|
}
|
|
|
|
|
2017-03-30 07:44:20 +01:00
|
|
|
static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
|
|
|
|
{
|
|
|
|
return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
|
|
|
|
}
|
|
|
|
|
2017-06-07 00:01:38 +01:00
|
|
|
uint32_t radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, bool has_tess);
|
|
|
|
struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
int idx);
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_graphics_pipeline_create_info {
|
|
|
|
bool use_rectlist;
|
|
|
|
bool db_depth_clear;
|
|
|
|
bool db_stencil_clear;
|
|
|
|
bool db_depth_disable_expclear;
|
|
|
|
bool db_stencil_disable_expclear;
|
|
|
|
bool db_flush_depth_inplace;
|
|
|
|
bool db_flush_stencil_inplace;
|
|
|
|
bool db_resummarize;
|
|
|
|
uint32_t custom_blend_mode;
|
|
|
|
};
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
|
|
|
|
struct radv_pipeline_cache *cache,
|
|
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
|
|
|
const struct radv_graphics_pipeline_create_info *extra,
|
|
|
|
const VkAllocationCallbacks *alloc);
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_graphics_pipeline_create(VkDevice device,
|
|
|
|
VkPipelineCache cache,
|
|
|
|
const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
|
|
|
const struct radv_graphics_pipeline_create_info *extra,
|
|
|
|
const VkAllocationCallbacks *alloc,
|
|
|
|
VkPipeline *pPipeline);
|
|
|
|
|
|
|
|
struct vk_format_description;
|
|
|
|
uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
|
|
|
|
int first_non_void);
|
|
|
|
uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
|
|
|
|
int first_non_void);
|
|
|
|
uint32_t radv_translate_colorformat(VkFormat format);
|
|
|
|
uint32_t radv_translate_color_numformat(VkFormat format,
|
|
|
|
const struct vk_format_description *desc,
|
|
|
|
int first_non_void);
|
|
|
|
uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
|
|
|
|
unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
|
|
|
|
uint32_t radv_translate_dbformat(VkFormat format);
|
|
|
|
uint32_t radv_translate_tex_dataformat(VkFormat format,
|
|
|
|
const struct vk_format_description *desc,
|
|
|
|
int first_non_void);
|
|
|
|
uint32_t radv_translate_tex_numformat(VkFormat format,
|
|
|
|
const struct vk_format_description *desc,
|
|
|
|
int first_non_void);
|
|
|
|
bool radv_format_pack_clear_color(VkFormat format,
|
|
|
|
uint32_t clear_vals[2],
|
|
|
|
VkClearColorValue *value);
|
|
|
|
bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
|
|
|
|
|
|
|
|
struct radv_fmask_info {
|
|
|
|
uint64_t offset;
|
|
|
|
uint64_t size;
|
|
|
|
unsigned alignment;
|
|
|
|
unsigned pitch_in_pixels;
|
|
|
|
unsigned bank_height;
|
|
|
|
unsigned slice_tile_max;
|
|
|
|
unsigned tile_mode_index;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_cmask_info {
|
|
|
|
uint64_t offset;
|
|
|
|
uint64_t size;
|
|
|
|
unsigned alignment;
|
|
|
|
unsigned slice_tile_max;
|
|
|
|
unsigned base_address_reg;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct r600_htile_info {
|
|
|
|
uint64_t offset;
|
|
|
|
uint64_t size;
|
|
|
|
unsigned pitch;
|
|
|
|
unsigned height;
|
|
|
|
unsigned xalign;
|
|
|
|
unsigned yalign;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_image {
|
|
|
|
VkImageType type;
|
|
|
|
/* The original VkFormat provided by the client. This may not match any
|
|
|
|
* of the actual surface formats.
|
|
|
|
*/
|
|
|
|
VkFormat vk_format;
|
|
|
|
VkImageAspectFlags aspects;
|
2017-05-10 22:01:00 +01:00
|
|
|
struct ac_surf_info info;
|
2016-10-07 00:16:09 +01:00
|
|
|
VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
|
|
|
|
VkImageTiling tiling; /** VkImageCreateInfo::tiling */
|
2017-02-04 14:56:20 +00:00
|
|
|
VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
|
2016-10-07 00:16:09 +01:00
|
|
|
|
|
|
|
VkDeviceSize size;
|
|
|
|
uint32_t alignment;
|
|
|
|
|
2016-12-17 20:25:32 +00:00
|
|
|
bool exclusive;
|
|
|
|
unsigned queue_family_mask;
|
|
|
|
|
2017-07-15 01:08:01 +01:00
|
|
|
bool shareable;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
/* Set when bound */
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
VkDeviceSize offset;
|
|
|
|
uint32_t dcc_offset;
|
2017-03-06 23:58:04 +00:00
|
|
|
uint32_t htile_offset;
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radeon_surf surface;
|
|
|
|
|
|
|
|
struct radv_fmask_info fmask;
|
|
|
|
struct radv_cmask_info cmask;
|
|
|
|
uint32_t clear_value_offset;
|
2017-03-02 21:39:10 +00:00
|
|
|
uint32_t dcc_pred_offset;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2017-05-15 00:23:24 +01:00
|
|
|
/* Whether the image has a htile that is known consistent with the contents of
|
|
|
|
* the image. */
|
2016-10-07 00:16:09 +01:00
|
|
|
bool radv_layout_has_htile(const struct radv_image *image,
|
2017-05-15 22:00:17 +01:00
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask);
|
2017-05-15 00:23:24 +01:00
|
|
|
|
|
|
|
/* Whether the image has a htile that is known consistent with the contents of
|
|
|
|
* the image and is allowed to be in compressed form.
|
|
|
|
*
|
|
|
|
* If this is false reads that don't use the htile should be able to return
|
|
|
|
* correct results.
|
|
|
|
*/
|
2016-10-07 00:16:09 +01:00
|
|
|
bool radv_layout_is_htile_compressed(const struct radv_image *image,
|
2017-05-15 22:00:17 +01:00
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask);
|
2017-05-15 00:23:24 +01:00
|
|
|
|
2016-12-26 23:57:36 +00:00
|
|
|
bool radv_layout_can_fast_clear(const struct radv_image *image,
|
|
|
|
VkImageLayout layout,
|
|
|
|
unsigned queue_mask);
|
2016-12-17 20:25:32 +00:00
|
|
|
|
|
|
|
|
2017-01-31 05:18:33 +00:00
|
|
|
unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
|
2016-12-17 20:25:32 +00:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
static inline uint32_t
|
|
|
|
radv_get_layerCount(const struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *range)
|
|
|
|
{
|
|
|
|
return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
|
2017-05-02 00:49:14 +01:00
|
|
|
image->info.array_size - range->baseArrayLayer : range->layerCount;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t
|
|
|
|
radv_get_levelCount(const struct radv_image *image,
|
|
|
|
const VkImageSubresourceRange *range)
|
|
|
|
{
|
|
|
|
return range->levelCount == VK_REMAINING_MIP_LEVELS ?
|
2017-05-02 00:49:14 +01:00
|
|
|
image->info.levels - range->baseMipLevel : range->levelCount;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
struct radeon_bo_metadata;
|
|
|
|
void
|
|
|
|
radv_init_metadata(struct radv_device *device,
|
|
|
|
struct radv_image *image,
|
|
|
|
struct radeon_bo_metadata *metadata);
|
|
|
|
|
|
|
|
struct radv_image_view {
|
|
|
|
struct radv_image *image; /**< VkImageViewCreateInfo::image */
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
|
|
|
|
VkImageViewType type;
|
|
|
|
VkImageAspectFlags aspect_mask;
|
|
|
|
VkFormat vk_format;
|
|
|
|
uint32_t base_layer;
|
|
|
|
uint32_t layer_count;
|
|
|
|
uint32_t base_mip;
|
|
|
|
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
|
|
|
|
|
|
|
|
uint32_t descriptor[8];
|
|
|
|
uint32_t fmask_descriptor[8];
|
2017-07-12 10:29:52 +01:00
|
|
|
|
|
|
|
/* Descriptor for use as a storage image as opposed to a sampled image.
|
|
|
|
* This has a few differences for cube maps (e.g. type).
|
|
|
|
*/
|
|
|
|
uint32_t storage_descriptor[8];
|
|
|
|
uint32_t storage_fmask_descriptor[8];
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_image_create_info {
|
|
|
|
const VkImageCreateInfo *vk_info;
|
|
|
|
bool scanout;
|
|
|
|
};
|
|
|
|
|
|
|
|
VkResult radv_image_create(VkDevice _device,
|
|
|
|
const struct radv_image_create_info *info,
|
|
|
|
const VkAllocationCallbacks* alloc,
|
|
|
|
VkImage *pImage);
|
|
|
|
|
|
|
|
void radv_image_view_init(struct radv_image_view *view,
|
|
|
|
struct radv_device *device,
|
2017-06-25 21:25:47 +01:00
|
|
|
const VkImageViewCreateInfo* pCreateInfo);
|
2017-04-28 08:06:09 +01:00
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_buffer_view {
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
VkFormat vk_format;
|
|
|
|
uint64_t range; /**< VkBufferViewCreateInfo::range */
|
|
|
|
uint32_t state[4];
|
|
|
|
};
|
|
|
|
void radv_buffer_view_init(struct radv_buffer_view *view,
|
|
|
|
struct radv_device *device,
|
|
|
|
const VkBufferViewCreateInfo* pCreateInfo,
|
|
|
|
struct radv_cmd_buffer *cmd_buffer);
|
|
|
|
|
|
|
|
static inline struct VkExtent3D
|
|
|
|
radv_sanitize_image_extent(const VkImageType imageType,
|
|
|
|
const struct VkExtent3D imageExtent)
|
|
|
|
{
|
|
|
|
switch (imageType) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
return (VkExtent3D) { imageExtent.width, 1, 1 };
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
return imageExtent;
|
|
|
|
default:
|
|
|
|
unreachable("invalid image type");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct VkOffset3D
|
|
|
|
radv_sanitize_image_offset(const VkImageType imageType,
|
|
|
|
const struct VkOffset3D imageOffset)
|
|
|
|
{
|
|
|
|
switch (imageType) {
|
|
|
|
case VK_IMAGE_TYPE_1D:
|
|
|
|
return (VkOffset3D) { imageOffset.x, 0, 0 };
|
|
|
|
case VK_IMAGE_TYPE_2D:
|
|
|
|
return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
|
|
|
|
case VK_IMAGE_TYPE_3D:
|
|
|
|
return imageOffset;
|
|
|
|
default:
|
|
|
|
unreachable("invalid image type");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-05-02 00:40:36 +01:00
|
|
|
static inline bool
|
|
|
|
radv_image_extent_compare(const struct radv_image *image,
|
|
|
|
const VkExtent3D *extent)
|
|
|
|
{
|
2017-05-02 00:49:14 +01:00
|
|
|
if (extent->width != image->info.width ||
|
|
|
|
extent->height != image->info.height ||
|
|
|
|
extent->depth != image->info.depth)
|
2017-05-02 00:40:36 +01:00
|
|
|
return false;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
struct radv_sampler {
|
|
|
|
uint32_t state[4];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_color_buffer_info {
|
2017-06-01 05:32:25 +01:00
|
|
|
uint64_t cb_color_base;
|
|
|
|
uint64_t cb_color_cmask;
|
|
|
|
uint64_t cb_color_fmask;
|
|
|
|
uint64_t cb_dcc_base;
|
2016-10-07 00:16:09 +01:00
|
|
|
uint32_t cb_color_pitch;
|
|
|
|
uint32_t cb_color_slice;
|
|
|
|
uint32_t cb_color_view;
|
|
|
|
uint32_t cb_color_info;
|
|
|
|
uint32_t cb_color_attrib;
|
2017-06-05 23:38:36 +01:00
|
|
|
uint32_t cb_color_attrib2;
|
2016-10-07 00:16:09 +01:00
|
|
|
uint32_t cb_dcc_control;
|
|
|
|
uint32_t cb_color_cmask_slice;
|
|
|
|
uint32_t cb_color_fmask_slice;
|
|
|
|
uint32_t cb_clear_value0;
|
|
|
|
uint32_t cb_clear_value1;
|
|
|
|
uint32_t micro_tile_mode;
|
2017-06-05 23:38:36 +01:00
|
|
|
uint32_t gfx9_epitch;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_ds_buffer_info {
|
2017-06-01 05:32:25 +01:00
|
|
|
uint64_t db_z_read_base;
|
|
|
|
uint64_t db_stencil_read_base;
|
|
|
|
uint64_t db_z_write_base;
|
|
|
|
uint64_t db_stencil_write_base;
|
|
|
|
uint64_t db_htile_data_base;
|
2016-10-07 00:16:09 +01:00
|
|
|
uint32_t db_depth_info;
|
|
|
|
uint32_t db_z_info;
|
|
|
|
uint32_t db_stencil_info;
|
|
|
|
uint32_t db_depth_view;
|
|
|
|
uint32_t db_depth_size;
|
|
|
|
uint32_t db_depth_slice;
|
|
|
|
uint32_t db_htile_surface;
|
|
|
|
uint32_t pa_su_poly_offset_db_fmt_cntl;
|
2017-06-05 23:39:44 +01:00
|
|
|
uint32_t db_z_info2;
|
|
|
|
uint32_t db_stencil_info2;
|
2016-10-07 00:16:09 +01:00
|
|
|
float offset_scale;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_attachment_info {
|
|
|
|
union {
|
|
|
|
struct radv_color_buffer_info cb;
|
|
|
|
struct radv_ds_buffer_info ds;
|
|
|
|
};
|
|
|
|
struct radv_image_view *attachment;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_framebuffer {
|
|
|
|
uint32_t width;
|
|
|
|
uint32_t height;
|
|
|
|
uint32_t layers;
|
|
|
|
|
|
|
|
uint32_t attachment_count;
|
|
|
|
struct radv_attachment_info attachments[0];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_subpass_barrier {
|
|
|
|
VkPipelineStageFlags src_stage_mask;
|
|
|
|
VkAccessFlags src_access_mask;
|
|
|
|
VkAccessFlags dst_access_mask;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_subpass {
|
|
|
|
uint32_t input_count;
|
|
|
|
uint32_t color_count;
|
2017-05-02 01:32:02 +01:00
|
|
|
VkAttachmentReference * input_attachments;
|
2016-10-07 00:16:09 +01:00
|
|
|
VkAttachmentReference * color_attachments;
|
|
|
|
VkAttachmentReference * resolve_attachments;
|
|
|
|
VkAttachmentReference depth_stencil_attachment;
|
|
|
|
|
|
|
|
/** Subpass has at least one resolve attachment */
|
|
|
|
bool has_resolve;
|
|
|
|
|
|
|
|
struct radv_subpass_barrier start_barrier;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_render_pass_attachment {
|
|
|
|
VkFormat format;
|
|
|
|
uint32_t samples;
|
|
|
|
VkAttachmentLoadOp load_op;
|
|
|
|
VkAttachmentLoadOp stencil_load_op;
|
|
|
|
VkImageLayout initial_layout;
|
|
|
|
VkImageLayout final_layout;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_render_pass {
|
|
|
|
uint32_t attachment_count;
|
|
|
|
uint32_t subpass_count;
|
|
|
|
VkAttachmentReference * subpass_attachments;
|
|
|
|
struct radv_render_pass_attachment * attachments;
|
|
|
|
struct radv_subpass_barrier end_barrier;
|
|
|
|
struct radv_subpass subpasses[0];
|
|
|
|
};
|
|
|
|
|
|
|
|
VkResult radv_device_init_meta(struct radv_device *device);
|
|
|
|
void radv_device_finish_meta(struct radv_device *device);
|
|
|
|
|
|
|
|
struct radv_query_pool {
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
uint32_t stride;
|
|
|
|
uint32_t availability_offset;
|
|
|
|
char *ptr;
|
|
|
|
VkQueryType type;
|
2017-04-10 21:20:19 +01:00
|
|
|
uint32_t pipeline_stats_mask;
|
2016-10-07 00:16:09 +01:00
|
|
|
};
|
|
|
|
|
2017-03-29 17:08:06 +01:00
|
|
|
void
|
|
|
|
radv_update_descriptor_sets(struct radv_device *device,
|
|
|
|
struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
VkDescriptorSet overrideSet,
|
|
|
|
uint32_t descriptorWriteCount,
|
|
|
|
const VkWriteDescriptorSet *pDescriptorWrites,
|
|
|
|
uint32_t descriptorCopyCount,
|
|
|
|
const VkCopyDescriptorSet *pDescriptorCopies);
|
|
|
|
|
2017-03-29 18:19:47 +01:00
|
|
|
void
|
|
|
|
radv_update_descriptor_set_with_template(struct radv_device *device,
|
|
|
|
struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_descriptor_set *set,
|
|
|
|
VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
|
|
|
|
const void *pData);
|
|
|
|
|
2017-04-13 23:26:58 +01:00
|
|
|
void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
VkPipelineBindPoint pipelineBindPoint,
|
|
|
|
VkPipelineLayout _layout,
|
|
|
|
uint32_t set,
|
|
|
|
uint32_t descriptorWriteCount,
|
|
|
|
const VkWriteDescriptorSet *pDescriptorWrites);
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *image, uint32_t value);
|
|
|
|
void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *image, uint32_t value);
|
2016-10-25 19:31:41 +01:00
|
|
|
|
|
|
|
struct radv_fence {
|
|
|
|
struct radeon_winsys_fence *fence;
|
|
|
|
bool submitted;
|
|
|
|
bool signalled;
|
|
|
|
};
|
|
|
|
|
2017-03-05 21:04:50 +00:00
|
|
|
struct radeon_winsys_sem;
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
#define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
|
|
|
|
\
|
|
|
|
static inline struct __radv_type * \
|
|
|
|
__radv_type ## _from_handle(__VkType _handle) \
|
|
|
|
{ \
|
|
|
|
return (struct __radv_type *) _handle; \
|
|
|
|
} \
|
|
|
|
\
|
|
|
|
static inline __VkType \
|
|
|
|
__radv_type ## _to_handle(struct __radv_type *_obj) \
|
|
|
|
{ \
|
|
|
|
return (__VkType) _obj; \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
|
|
|
|
\
|
|
|
|
static inline struct __radv_type * \
|
|
|
|
__radv_type ## _from_handle(__VkType _handle) \
|
|
|
|
{ \
|
|
|
|
return (struct __radv_type *)(uintptr_t) _handle; \
|
|
|
|
} \
|
|
|
|
\
|
|
|
|
static inline __VkType \
|
|
|
|
__radv_type ## _to_handle(struct __radv_type *_obj) \
|
|
|
|
{ \
|
|
|
|
return (__VkType)(uintptr_t) _obj; \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
|
|
|
|
struct __radv_type *__name = __radv_type ## _from_handle(__handle)
|
|
|
|
|
|
|
|
RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
|
|
|
|
RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
|
|
|
|
RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
|
|
|
|
RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
|
|
|
|
RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
|
|
|
|
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
|
2017-03-29 18:19:47 +01:00
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
|
2016-10-07 00:16:09 +01:00
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
|
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
|
2017-03-05 21:04:50 +00:00
|
|
|
RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
|
2016-10-07 00:16:09 +01:00
|
|
|
|
2016-10-07 12:19:19 +01:00
|
|
|
#endif /* RADV_PRIVATE_H */
|