2021-02-08 02:10:08 +00:00
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/*
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* Copyright (C) 2020 Google, Inc.
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* Copyright (C) 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/**
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* Return the intrinsic if it matches the mask in "modes", else return NULL.
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*/
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static nir_intrinsic_instr *
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get_io_intrinsic(nir_instr *instr, nir_variable_mode modes,
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nir_variable_mode *out_mode)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return NULL;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_load_input:
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case nir_intrinsic_load_input_vertex:
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case nir_intrinsic_load_interpolated_input:
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case nir_intrinsic_load_per_vertex_input:
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*out_mode = nir_var_shader_in;
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return modes & nir_var_shader_in ? intr : NULL;
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case nir_intrinsic_load_output:
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case nir_intrinsic_load_per_vertex_output:
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_vertex_output:
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*out_mode = nir_var_shader_out;
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return modes & nir_var_shader_out ? intr : NULL;
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default:
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return NULL;
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}
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}
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/**
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* Recompute the IO "base" indices from scratch to remove holes or to fix
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* incorrect base values due to changes in IO locations by using IO locations
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* to assign new bases. The mapping from locations to bases becomes
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* monotonically increasing.
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*/
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bool
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2022-01-04 17:34:23 +00:00
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nir_recompute_io_bases(nir_shader *nir, nir_variable_mode modes)
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2021-02-08 02:10:08 +00:00
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{
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2022-01-04 17:34:23 +00:00
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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2021-02-08 02:10:08 +00:00
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BITSET_DECLARE(inputs, NUM_TOTAL_VARYING_SLOTS);
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BITSET_DECLARE(outputs, NUM_TOTAL_VARYING_SLOTS);
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BITSET_ZERO(inputs);
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BITSET_ZERO(outputs);
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/* Gather the bitmasks of used locations. */
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nir_foreach_block_safe (block, impl) {
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nir_foreach_instr_safe (instr, block) {
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nir_variable_mode mode;
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nir_intrinsic_instr *intr = get_io_intrinsic(instr, modes, &mode);
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if (!intr)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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unsigned num_slots = sem.num_slots;
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if (sem.medium_precision)
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num_slots = (num_slots + sem.high_16bits + 1) / 2;
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if (mode == nir_var_shader_in) {
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for (unsigned i = 0; i < num_slots; i++)
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BITSET_SET(inputs, sem.location + i);
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} else if (!sem.dual_source_blend_index) {
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for (unsigned i = 0; i < num_slots; i++)
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BITSET_SET(outputs, sem.location + i);
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}
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}
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}
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/* Renumber bases. */
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bool changed = false;
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nir_foreach_block_safe (block, impl) {
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nir_foreach_instr_safe (instr, block) {
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nir_variable_mode mode;
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nir_intrinsic_instr *intr = get_io_intrinsic(instr, modes, &mode);
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if (!intr)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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unsigned num_slots = sem.num_slots;
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if (sem.medium_precision)
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num_slots = (num_slots + sem.high_16bits + 1) / 2;
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if (mode == nir_var_shader_in) {
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nir_intrinsic_set_base(intr,
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BITSET_PREFIX_SUM(inputs, sem.location));
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} else if (sem.dual_source_blend_index) {
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nir_intrinsic_set_base(intr,
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BITSET_PREFIX_SUM(outputs, NUM_TOTAL_VARYING_SLOTS));
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} else {
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nir_intrinsic_set_base(intr,
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BITSET_PREFIX_SUM(outputs, sem.location));
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}
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changed = true;
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}
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}
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2021-07-06 17:55:23 +01:00
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if (changed) {
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nir_metadata_preserve(impl, nir_metadata_dominance |
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nir_metadata_block_index);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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2021-02-08 02:10:08 +00:00
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return changed;
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}
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/**
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* Lower mediump inputs and/or outputs to 16 bits.
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*
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* \param modes Whether to lower inputs, outputs, or both.
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* \param varying_mask Determines which varyings to skip (VS inputs,
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* FS outputs, and patch varyings ignore this mask).
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* \param use_16bit_slots Remap lowered slots to* VARYING_SLOT_VARn_16BIT.
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*/
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bool
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nir_lower_mediump_io(nir_shader *nir, nir_variable_mode modes,
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uint64_t varying_mask, bool use_16bit_slots)
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{
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bool changed = false;
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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assert(impl);
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nir_builder b;
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nir_builder_init(&b, impl);
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nir_foreach_block_safe (block, impl) {
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nir_foreach_instr_safe (instr, block) {
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nir_variable_mode mode;
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nir_intrinsic_instr *intr = get_io_intrinsic(instr, modes, &mode);
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if (!intr)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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nir_ssa_def *(*convert)(nir_builder *, nir_ssa_def *);
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bool is_varying = !(nir->info.stage == MESA_SHADER_VERTEX &&
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mode == nir_var_shader_in) &&
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!(nir->info.stage == MESA_SHADER_FRAGMENT &&
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mode == nir_var_shader_out);
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if (!sem.medium_precision ||
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(is_varying && sem.location <= VARYING_SLOT_VAR31 &&
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!(varying_mask & BITFIELD64_BIT(sem.location))))
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continue; /* can't lower */
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if (nir_intrinsic_has_src_type(intr)) {
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/* Stores. */
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nir_alu_type type = nir_intrinsic_src_type(intr);
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switch (type) {
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case nir_type_float32:
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convert = nir_f2fmp;
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break;
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case nir_type_int32:
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case nir_type_uint32:
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convert = nir_i2imp;
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break;
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default:
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continue; /* already lowered? */
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}
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/* Convert the 32-bit store into a 16-bit store. */
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b.cursor = nir_before_instr(&intr->instr);
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nir_instr_rewrite_src_ssa(&intr->instr, &intr->src[0],
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convert(&b, intr->src[0].ssa));
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nir_intrinsic_set_src_type(intr, (type & ~32) | 16);
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} else {
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/* Loads. */
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nir_alu_type type = nir_intrinsic_dest_type(intr);
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switch (type) {
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case nir_type_float32:
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convert = nir_f2f32;
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break;
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case nir_type_int32:
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convert = nir_i2i32;
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break;
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case nir_type_uint32:
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convert = nir_u2u32;
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break;
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default:
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continue; /* already lowered? */
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}
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/* Convert the 32-bit load into a 16-bit load. */
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b.cursor = nir_after_instr(&intr->instr);
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intr->dest.ssa.bit_size = 16;
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nir_intrinsic_set_dest_type(intr, (type & ~32) | 16);
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nir_ssa_def *dst = convert(&b, &intr->dest.ssa);
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nir_ssa_def_rewrite_uses_after(&intr->dest.ssa, dst,
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dst->parent_instr);
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}
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if (use_16bit_slots && is_varying &&
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sem.location >= VARYING_SLOT_VAR0 &&
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sem.location <= VARYING_SLOT_VAR31) {
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unsigned index = sem.location - VARYING_SLOT_VAR0;
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sem.location = VARYING_SLOT_VAR0_16BIT + index / 2;
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sem.high_16bits = index % 2;
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nir_intrinsic_set_io_semantics(intr, sem);
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}
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changed = true;
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}
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}
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2021-06-16 19:54:46 +01:00
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if (changed && use_16bit_slots)
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2022-01-04 17:34:23 +00:00
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nir_recompute_io_bases(nir, modes);
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2021-02-08 02:10:08 +00:00
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2021-07-06 17:55:23 +01:00
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if (changed) {
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nir_metadata_preserve(impl, nir_metadata_dominance |
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nir_metadata_block_index);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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2021-02-08 02:10:08 +00:00
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return changed;
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}
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/**
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* Set the mediump precision bit for those shader inputs and outputs that are
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* set in the "modes" mask. Non-generic varyings (that GLES3 doesn't have)
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* are ignored. The "types" mask can be (nir_type_float | nir_type_int), etc.
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*/
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bool
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nir_force_mediump_io(nir_shader *nir, nir_variable_mode modes,
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nir_alu_type types)
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{
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bool changed = false;
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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assert(impl);
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nir_builder b;
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nir_builder_init(&b, impl);
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nir_foreach_block_safe (block, impl) {
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nir_foreach_instr_safe (instr, block) {
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nir_variable_mode mode;
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nir_intrinsic_instr *intr = get_io_intrinsic(instr, modes, &mode);
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if (!intr)
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continue;
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nir_alu_type type;
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if (nir_intrinsic_has_src_type(intr))
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type = nir_intrinsic_src_type(intr);
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else
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type = nir_intrinsic_dest_type(intr);
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if (!(type & types))
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (nir->info.stage == MESA_SHADER_FRAGMENT &&
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mode == nir_var_shader_out) {
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/* Only accept FS outputs. */
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if (sem.location < FRAG_RESULT_DATA0 &&
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sem.location != FRAG_RESULT_COLOR)
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continue;
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} else if (nir->info.stage == MESA_SHADER_VERTEX &&
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mode == nir_var_shader_in) {
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/* Accept all VS inputs. */
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} else {
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/* Only accept generic varyings. */
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if (sem.location < VARYING_SLOT_VAR0 ||
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sem.location > VARYING_SLOT_VAR31)
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continue;
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}
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sem.medium_precision = 1;
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nir_intrinsic_set_io_semantics(intr, sem);
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changed = true;
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}
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}
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2021-07-06 17:55:23 +01:00
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if (changed) {
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nir_metadata_preserve(impl, nir_metadata_dominance |
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nir_metadata_block_index);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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2021-02-08 02:10:08 +00:00
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return changed;
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}
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/**
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* Remap 16-bit varying slots to the original 32-bit varying slots.
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* This only changes IO semantics and bases.
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*/
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bool
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nir_unpack_16bit_varying_slots(nir_shader *nir, nir_variable_mode modes)
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{
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bool changed = false;
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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assert(impl);
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nir_foreach_block_safe (block, impl) {
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nir_foreach_instr_safe (instr, block) {
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nir_variable_mode mode;
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nir_intrinsic_instr *intr = get_io_intrinsic(instr, modes, &mode);
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if (!intr)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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if (sem.location < VARYING_SLOT_VAR0_16BIT ||
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sem.location > VARYING_SLOT_VAR15_16BIT)
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continue;
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sem.location = VARYING_SLOT_VAR0 +
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(sem.location - VARYING_SLOT_VAR0_16BIT) * 2 +
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sem.high_16bits;
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sem.high_16bits = 0;
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nir_intrinsic_set_io_semantics(intr, sem);
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changed = true;
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}
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}
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if (changed)
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2022-01-04 17:34:23 +00:00
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|
|
nir_recompute_io_bases(nir, modes);
|
2021-02-08 02:10:08 +00:00
|
|
|
|
2021-07-06 17:55:23 +01:00
|
|
|
if (changed) {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_dominance |
|
|
|
|
nir_metadata_block_index);
|
|
|
|
} else {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_all);
|
|
|
|
}
|
|
|
|
|
2021-02-08 02:10:08 +00:00
|
|
|
return changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_n_to_m_conversion(nir_instr *instr, unsigned n, nir_op m)
|
|
|
|
{
|
|
|
|
if (instr->type != nir_instr_type_alu)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
nir_alu_instr *alu = nir_instr_as_alu(instr);
|
|
|
|
return alu->op == m && alu->src[0].src.ssa->bit_size == n;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_f16_to_f32_conversion(nir_instr *instr)
|
|
|
|
{
|
|
|
|
return is_n_to_m_conversion(instr, 16, nir_op_f2f32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_f32_to_f16_conversion(nir_instr *instr)
|
|
|
|
{
|
|
|
|
return is_n_to_m_conversion(instr, 32, nir_op_f2f16) ||
|
|
|
|
is_n_to_m_conversion(instr, 32, nir_op_f2f16_rtne) ||
|
|
|
|
is_n_to_m_conversion(instr, 32, nir_op_f2fmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_i16_to_i32_conversion(nir_instr *instr)
|
|
|
|
{
|
|
|
|
return is_n_to_m_conversion(instr, 16, nir_op_i2i32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_u16_to_u32_conversion(nir_instr *instr)
|
|
|
|
{
|
|
|
|
return is_n_to_m_conversion(instr, 16, nir_op_u2u32);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
is_i32_to_i16_conversion(nir_instr *instr)
|
|
|
|
{
|
2022-02-05 11:08:27 +00:00
|
|
|
return is_n_to_m_conversion(instr, 32, nir_op_i2i16) ||
|
|
|
|
is_n_to_m_conversion(instr, 32, nir_op_u2u16);
|
2021-02-08 02:10:08 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
replace_with_mov(nir_builder *b, nir_instr *instr, nir_src *src,
|
|
|
|
nir_alu_instr *alu)
|
|
|
|
{
|
|
|
|
nir_ssa_def *mov = nir_mov_alu(b, alu->src[0],
|
|
|
|
nir_dest_num_components(alu->dest.dest));
|
|
|
|
assert(!alu->dest.saturate);
|
|
|
|
nir_instr_rewrite_src_ssa(instr, src, mov);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* If texture source operands use f16->f32 conversions or return values are
|
|
|
|
* followed by f16->f32 or f32->f16, remove those conversions. This benefits
|
|
|
|
* drivers that have texture opcodes that can accept and return 16-bit types.
|
|
|
|
*
|
|
|
|
* "tex_src_types" is a mask of nir_tex_src_* operands that should be handled.
|
|
|
|
* It's always done for the destination.
|
|
|
|
*
|
|
|
|
* This should be run after late algebraic optimizations.
|
|
|
|
* Copy propagation and DCE should be run after this.
|
|
|
|
*/
|
|
|
|
bool
|
|
|
|
nir_fold_16bit_sampler_conversions(nir_shader *nir,
|
|
|
|
unsigned tex_src_types)
|
|
|
|
{
|
|
|
|
bool changed = false;
|
|
|
|
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
|
|
|
|
assert(impl);
|
|
|
|
|
|
|
|
nir_builder b;
|
|
|
|
nir_builder_init(&b, impl);
|
|
|
|
|
|
|
|
nir_foreach_block_safe (block, impl) {
|
|
|
|
nir_foreach_instr_safe (instr, block) {
|
|
|
|
if (instr->type != nir_instr_type_tex)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
nir_tex_instr *tex = nir_instr_as_tex(instr);
|
|
|
|
nir_instr *src;
|
|
|
|
nir_alu_instr *src_alu;
|
|
|
|
|
2021-11-02 13:29:47 +00:00
|
|
|
/* Skip sparse residency */
|
|
|
|
if (tex->is_sparse)
|
|
|
|
continue;
|
|
|
|
|
2021-02-08 02:10:08 +00:00
|
|
|
/* Skip because AMD doesn't support 16-bit types with these. */
|
|
|
|
if ((tex->op == nir_texop_txs ||
|
|
|
|
tex->op == nir_texop_query_levels) ||
|
|
|
|
tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Optimize source operands. */
|
|
|
|
for (unsigned i = 0; i < tex->num_srcs; i++) {
|
|
|
|
/* Filter out sources that should be ignored. */
|
|
|
|
if (!(BITFIELD_BIT(tex->src[i].src_type) & tex_src_types))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
src = tex->src[i].src.ssa->parent_instr;
|
|
|
|
if (src->type != nir_instr_type_alu)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
src_alu = nir_instr_as_alu(src);
|
|
|
|
b.cursor = nir_before_instr(src);
|
|
|
|
|
|
|
|
if (src_alu->op == nir_op_mov) {
|
|
|
|
assert(!"The IR shouldn't contain any movs to make this pass"
|
|
|
|
" effective.");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Handle vector sources that are made of scalar instructions. */
|
|
|
|
if (nir_op_is_vec(src_alu->op)) {
|
|
|
|
/* See if the vector is made of f16->f32 opcodes. */
|
|
|
|
unsigned num = nir_dest_num_components(src_alu->dest.dest);
|
|
|
|
bool is_f16_to_f32 = true;
|
|
|
|
bool is_u16_to_u32 = true;
|
|
|
|
|
|
|
|
for (unsigned comp = 0; comp < num; comp++) {
|
|
|
|
nir_instr *instr = src_alu->src[comp].src.ssa->parent_instr;
|
|
|
|
is_f16_to_f32 &= is_f16_to_f32_conversion(instr);
|
|
|
|
/* Zero-extension (u16) and sign-extension (i16) have
|
|
|
|
* the same behavior here - txf returns 0 if bit 15 is set
|
|
|
|
* because it's out of bounds and the higher bits don't
|
|
|
|
* matter.
|
|
|
|
*/
|
|
|
|
is_u16_to_u32 &= is_u16_to_u32_conversion(instr) ||
|
|
|
|
is_i16_to_i32_conversion(instr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!is_f16_to_f32 && !is_u16_to_u32)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
nir_alu_instr *new_vec = nir_alu_instr_clone(nir, src_alu);
|
|
|
|
nir_instr_insert_after(&src_alu->instr, &new_vec->instr);
|
|
|
|
|
|
|
|
/* Replace conversions with mov. */
|
|
|
|
for (unsigned comp = 0; comp < num; comp++) {
|
|
|
|
nir_instr *instr = new_vec->src[comp].src.ssa->parent_instr;
|
|
|
|
replace_with_mov(&b, &new_vec->instr,
|
|
|
|
&new_vec->src[comp].src,
|
|
|
|
nir_instr_as_alu(instr));
|
|
|
|
}
|
|
|
|
|
|
|
|
new_vec->dest.dest.ssa.bit_size =
|
|
|
|
new_vec->src[0].src.ssa->bit_size;
|
|
|
|
nir_instr_rewrite_src_ssa(&tex->instr, &tex->src[i].src,
|
|
|
|
&new_vec->dest.dest.ssa);
|
|
|
|
changed = true;
|
|
|
|
} else if (is_f16_to_f32_conversion(&src_alu->instr) ||
|
|
|
|
is_u16_to_u32_conversion(&src_alu->instr) ||
|
|
|
|
is_i16_to_i32_conversion(&src_alu->instr)) {
|
|
|
|
/* Handle scalar sources. */
|
|
|
|
replace_with_mov(&b, &tex->instr, &tex->src[i].src, src_alu);
|
|
|
|
changed = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Optimize the destination. */
|
|
|
|
bool is_f32_to_f16 = true;
|
|
|
|
bool is_i32_to_i16 = true; /* same behavior for int and uint */
|
|
|
|
|
|
|
|
nir_foreach_use(use, &tex->dest.ssa) {
|
|
|
|
is_f32_to_f16 &= is_f32_to_f16_conversion(use->parent_instr);
|
|
|
|
is_i32_to_i16 &= is_i32_to_i16_conversion(use->parent_instr);
|
|
|
|
}
|
|
|
|
|
2022-03-23 10:44:57 +00:00
|
|
|
if (is_f32_to_f16 || is_i32_to_i16) {
|
2021-02-08 02:10:08 +00:00
|
|
|
/* All uses are the same conversions. Replace them with mov. */
|
|
|
|
nir_foreach_use(use, &tex->dest.ssa) {
|
|
|
|
nir_alu_instr *conv = nir_instr_as_alu(use->parent_instr);
|
|
|
|
conv->op = nir_op_mov;
|
|
|
|
tex->dest.ssa.bit_size = conv->dest.dest.ssa.bit_size;
|
|
|
|
tex->dest_type = (tex->dest_type & (~16 & ~32 & ~64)) |
|
|
|
|
conv->dest.dest.ssa.bit_size;
|
|
|
|
}
|
|
|
|
changed = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-07-06 17:55:23 +01:00
|
|
|
if (changed) {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_dominance |
|
|
|
|
nir_metadata_block_index);
|
|
|
|
} else {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_all);
|
|
|
|
}
|
|
|
|
|
2021-02-08 02:10:08 +00:00
|
|
|
return changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Fix types of source operands of texture opcodes according to
|
|
|
|
* the constraints by inserting the appropriate conversion opcodes.
|
|
|
|
*
|
|
|
|
* For example, if the type of derivatives must be equal to texture
|
|
|
|
* coordinates and the type of the texture bias must be 32-bit, there
|
|
|
|
* will be 2 constraints describing that.
|
|
|
|
*/
|
|
|
|
bool
|
|
|
|
nir_legalize_16bit_sampler_srcs(nir_shader *nir,
|
|
|
|
nir_tex_src_type_constraints constraints)
|
|
|
|
{
|
|
|
|
bool changed = false;
|
|
|
|
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
|
|
|
|
assert(impl);
|
|
|
|
|
|
|
|
nir_builder b;
|
|
|
|
nir_builder_init(&b, impl);
|
|
|
|
|
|
|
|
nir_foreach_block_safe (block, impl) {
|
|
|
|
nir_foreach_instr_safe (instr, block) {
|
|
|
|
if (instr->type != nir_instr_type_tex)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
nir_tex_instr *tex = nir_instr_as_tex(instr);
|
|
|
|
int8_t map[nir_num_tex_src_types];
|
|
|
|
memset(map, -1, sizeof(map));
|
|
|
|
|
|
|
|
/* Create a mapping from src_type to src[i]. */
|
|
|
|
for (unsigned i = 0; i < tex->num_srcs; i++)
|
|
|
|
map[tex->src[i].src_type] = i;
|
|
|
|
|
|
|
|
/* Legalize src types. */
|
|
|
|
for (unsigned i = 0; i < tex->num_srcs; i++) {
|
|
|
|
nir_tex_src_type_constraint c = constraints[tex->src[i].src_type];
|
|
|
|
|
|
|
|
if (!c.legalize_type)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Determine the required bit size for the src. */
|
|
|
|
unsigned bit_size;
|
|
|
|
if (c.bit_size) {
|
|
|
|
bit_size = c.bit_size;
|
|
|
|
} else {
|
|
|
|
if (map[c.match_src] == -1)
|
|
|
|
continue; /* e.g. txs */
|
|
|
|
|
|
|
|
bit_size = tex->src[map[c.match_src]].src.ssa->bit_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if the type is legal. */
|
|
|
|
if (bit_size == tex->src[i].src.ssa->bit_size)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Fix the bit size. */
|
|
|
|
bool is_sint = i == nir_tex_src_offset;
|
|
|
|
bool is_uint = !is_sint &&
|
|
|
|
(tex->op == nir_texop_txf ||
|
|
|
|
tex->op == nir_texop_txf_ms ||
|
|
|
|
tex->op == nir_texop_txs ||
|
|
|
|
tex->op == nir_texop_samples_identical);
|
|
|
|
nir_ssa_def *(*convert)(nir_builder *, nir_ssa_def *);
|
|
|
|
|
|
|
|
switch (bit_size) {
|
|
|
|
case 16:
|
|
|
|
convert = is_sint ? nir_i2i16 :
|
|
|
|
is_uint ? nir_u2u16 : nir_f2f16;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
convert = is_sint ? nir_i2i32 :
|
|
|
|
is_uint ? nir_u2u32 : nir_f2f32;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(!"unexpected bit size");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
b.cursor = nir_before_instr(&tex->instr);
|
|
|
|
nir_ssa_def *conv =
|
|
|
|
convert(&b, nir_ssa_for_src(&b, tex->src[i].src,
|
|
|
|
tex->src[i].src.ssa->num_components));
|
|
|
|
nir_instr_rewrite_src_ssa(&tex->instr, &tex->src[i].src, conv);
|
|
|
|
changed = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-07-06 17:55:23 +01:00
|
|
|
if (changed) {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_dominance |
|
|
|
|
nir_metadata_block_index);
|
|
|
|
} else {
|
|
|
|
nir_metadata_preserve(impl, nir_metadata_all);
|
|
|
|
}
|
|
|
|
|
2021-02-08 02:10:08 +00:00
|
|
|
return changed;
|
|
|
|
}
|