2021-07-27 23:34:35 +01:00
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/*
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* Copyright (C) 2021 Collabora, Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "compiler.h"
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#include "util/u_memory.h"
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/* Validatation doesn't make sense in release builds */
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#ifndef NDEBUG
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/* Validate that all sources are initialized in all read components. This is
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* required for correct register allocation. We check a weaker condition, that
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* all sources that are read are written at some point (equivalently, the live
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* set is empty at the start of the program). TODO: Strengthen */
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bool
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bi_validate_initialization(bi_context *ctx)
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{
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bool success = true;
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/* Calculate the live set */
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bi_block *entry = bi_entry_block(ctx);
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2022-05-18 16:24:32 +01:00
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bi_compute_liveness_ssa(ctx);
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2021-07-27 23:34:35 +01:00
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/* Validate that the live set is indeed empty */
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2022-05-18 16:24:32 +01:00
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for (unsigned i = 0; i < ctx->ssa_alloc; ++i) {
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if (BITSET_TEST(entry->ssa_live_in, i)) {
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fprintf(stderr, "%u\n", i);
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success = false;
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}
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2021-07-27 23:34:35 +01:00
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}
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return success;
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}
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2022-05-11 20:47:39 +01:00
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/*
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* Validate that there are no bi_registers accessed except at the beginning of
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* the start block, and that preloads are unique. This ensures RA can coalesce
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* preloads without interference tracking.
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*/
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static bool
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bi_validate_preload(bi_context *ctx)
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{
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bool start = true;
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uint64_t preloaded = 0;
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bi_foreach_block(ctx, block) {
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bi_foreach_instr_in_block(block, I) {
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/* No instruction should have a register destination */
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bi_foreach_dest(I, d) {
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if (I->dest[d].type == BI_INDEX_REGISTER)
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return false;
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}
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/* Preloads are register moves at the start */
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bool is_preload =
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start && I->op == BI_OPCODE_MOV_I32 &&
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I->src[0].type == BI_INDEX_REGISTER;
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/* After the first nonpreload, we're done preloading */
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start &= is_preload;
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/* Only preloads may have a register source */
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bi_foreach_src(I, s) {
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if (I->src[s].type == BI_INDEX_REGISTER && !is_preload)
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return false;
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}
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/* Check uniqueness */
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if (is_preload) {
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unsigned r = I->src[0].value;
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if (preloaded & BITFIELD64_BIT(r))
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return false;
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preloaded |= BITFIELD64_BIT(r);
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}
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}
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/* Only the first block may preload */
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start = false;
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}
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return true;
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}
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2022-05-13 01:21:42 +01:00
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/*
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* Type check the dimensionality of sources and destinations. This occurs in two
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* passes, first to gather all destination sizes, second to validate all source
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* sizes. Depends on SSA form.
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*/
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static bool
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bi_validate_width(bi_context *ctx)
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{
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bool succ = true;
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uint8_t *width = calloc(ctx->ssa_alloc, sizeof(uint8_t));
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bi_foreach_instr_global(ctx, I) {
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bi_foreach_dest(I, d) {
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2022-07-26 17:25:19 +01:00
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assert(bi_is_ssa(I->dest[d]));
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2022-05-13 01:21:42 +01:00
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unsigned v = I->dest[d].value;
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assert(width[v] == 0 && "broken SSA");
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width[v] = bi_count_write_registers(I, d);
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}
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}
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bi_foreach_instr_global(ctx, I) {
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2022-07-26 17:22:34 +01:00
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bi_foreach_ssa_src(I, s) {
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2022-05-13 01:21:42 +01:00
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unsigned v = I->src[s].value;
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unsigned n = bi_count_read_registers(I, s);
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if (width[v] != n) {
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succ = false;
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fprintf(stderr,
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"source %u, expected width %u, got width %u\n",
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s, n, width[v]);
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bi_print_instr(I, stderr);
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fprintf(stderr, "\n");
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}
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}
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}
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free(width);
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return succ;
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}
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2022-07-21 16:53:23 +01:00
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/*
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2022-07-22 21:28:46 +01:00
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* Validate that all destinations of the instruction are present.
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2022-07-21 16:53:23 +01:00
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*/
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static bool
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2022-07-22 21:28:46 +01:00
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bi_validate_dest(bi_context *ctx)
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2022-07-21 16:53:23 +01:00
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{
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bool succ = true;
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bi_foreach_instr_global(ctx, I) {
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2022-07-22 21:28:46 +01:00
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bi_foreach_dest(I, d) {
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if (bi_is_null(I->dest[d])) {
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2022-07-21 16:53:23 +01:00
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succ = false;
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2022-07-22 21:28:46 +01:00
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fprintf(stderr, "expected dest %u", d);
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2022-07-21 16:53:23 +01:00
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bi_print_instr(I, stderr);
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fprintf(stderr, "\n");
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}
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}
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}
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return succ;
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}
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2022-05-13 22:53:53 +01:00
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/*
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* Validate that phis only appear at the beginning of blocks.
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*/
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static bool
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bi_validate_phi_ordering(bi_context *ctx)
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{
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bi_foreach_block(ctx, block) {
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bool start = true;
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bi_foreach_instr_in_block(block, I) {
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if (start)
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start = I->op == BI_OPCODE_PHI;
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else if (I->op == BI_OPCODE_PHI)
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return false;
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}
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}
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return true;
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}
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2021-07-27 23:34:35 +01:00
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void
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bi_validate(bi_context *ctx, const char *after)
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{
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bool fail = false;
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if (bifrost_debug & BIFROST_DBG_NOVALIDATE)
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return;
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if (!bi_validate_initialization(ctx)) {
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fprintf(stderr, "Uninitialized data read after %s\n", after);
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fail = true;
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}
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2022-05-11 20:47:39 +01:00
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if (!bi_validate_preload(ctx)) {
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fprintf(stderr, "Unexpected preload after %s\n", after);
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fail = true;
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}
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2022-05-13 01:21:42 +01:00
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if (!bi_validate_width(ctx)) {
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fprintf(stderr, "Unexpected vector with after %s\n", after);
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fail = true;
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}
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2021-07-27 23:34:35 +01:00
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2022-07-22 21:28:46 +01:00
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if (!bi_validate_dest(ctx)) {
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fprintf(stderr, "Unexpected source/dest after %s\n", after);
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2022-07-21 16:53:23 +01:00
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fail = true;
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}
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2022-05-13 22:53:53 +01:00
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if (!bi_validate_phi_ordering(ctx)) {
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fprintf(stderr, "Unexpected phi ordering after %s\n", after);
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fail = true;
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}
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2021-07-27 23:34:35 +01:00
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if (fail) {
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bi_print_shader(ctx, stderr);
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exit(1);
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}
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}
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#endif /* NDEBUG */
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