mirror of https://github.com/doitsujin/dxvk
[dxbc] Implemented basic control flow instuctions
This commit is contained in:
Philip Rebohle
parent
858913ec0c
commit
1e08c0744f
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@ -48,84 +48,37 @@ namespace dxvk {
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void DxbcCompiler::processInstruction(const DxbcShaderInstruction& ins) {
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switch (ins.op) {
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case DxbcOpcode::DclGlobalFlags:
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return this->emitDclGlobalFlags(ins);
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switch (ins.opClass) {
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case DxbcInstClass::Declaration:
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return this->emitDcl(ins);
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case DxbcOpcode::DclTemps:
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return this->emitDclTemps(ins);
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case DxbcInstClass::ControlFlow:
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return this->emitControlFlow(ins);
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case DxbcOpcode::DclInput:
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case DxbcOpcode::DclInputSgv:
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case DxbcOpcode::DclInputSiv:
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case DxbcOpcode::DclInputPs:
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case DxbcOpcode::DclInputPsSgv:
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case DxbcOpcode::DclInputPsSiv:
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case DxbcOpcode::DclOutput:
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case DxbcOpcode::DclOutputSgv:
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case DxbcOpcode::DclOutputSiv:
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return this->emitDclInterfaceReg(ins);
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case DxbcOpcode::DclConstantBuffer:
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return this->emitDclConstantBuffer(ins);
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case DxbcOpcode::DclSampler:
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return this->emitDclSampler(ins);
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case DxbcOpcode::DclResource:
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return this->emitDclResource(ins);
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case DxbcOpcode::Add:
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case DxbcOpcode::Div:
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case DxbcOpcode::Exp:
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case DxbcOpcode::Log:
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case DxbcOpcode::Mad:
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case DxbcOpcode::Max:
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case DxbcOpcode::Min:
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case DxbcOpcode::Mul:
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case DxbcOpcode::Mov:
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case DxbcOpcode::Rsq:
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case DxbcOpcode::Sqrt:
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case DxbcOpcode::IAdd:
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case DxbcOpcode::IMad:
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case DxbcOpcode::IMax:
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case DxbcOpcode::IMin:
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case DxbcOpcode::INeg:
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return this->emitVectorAlu(ins);
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case DxbcOpcode::Movc:
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return this->emitVectorCmov(ins);
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case DxbcOpcode::Eq:
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case DxbcOpcode::Ge:
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case DxbcOpcode::Lt:
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case DxbcOpcode::Ne:
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case DxbcOpcode::IEq:
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case DxbcOpcode::IGe:
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case DxbcOpcode::ILt:
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case DxbcOpcode::INe:
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return this->emitVectorCmp(ins);
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case DxbcOpcode::Dp2:
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case DxbcOpcode::Dp3:
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case DxbcOpcode::Dp4:
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return this->emitVectorDot(ins);
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case DxbcOpcode::IMul:
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return this->emitVectorImul(ins);
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case DxbcOpcode::SinCos:
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return this->emitVectorSinCos(ins);
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case DxbcOpcode::Sample:
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case DxbcInstClass::TextureSample:
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return this->emitSample(ins);
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case DxbcOpcode::Ret:
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return this->emitRet(ins);
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case DxbcInstClass::VectorAlu:
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return this->emitVectorAlu(ins);
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case DxbcInstClass::VectorCmov:
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return this->emitVectorCmov(ins);
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case DxbcInstClass::VectorCmp:
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return this->emitVectorCmp(ins);
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case DxbcInstClass::VectorDot:
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return this->emitVectorDot(ins);
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case DxbcInstClass::VectorImul:
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return this->emitVectorImul(ins);
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case DxbcInstClass::VectorSinCos:
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return this->emitVectorSinCos(ins);
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default:
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Logger::warn(
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str::format("DxbcCompiler: Unhandled opcode: ",
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str::format("DxbcCompiler: Unhandled opcode class: ",
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ins.op));
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}
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}
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@ -171,6 +124,42 @@ namespace dxvk {
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}
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void DxbcCompiler::emitDcl(const DxbcShaderInstruction& ins) {
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switch (ins.op) {
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case DxbcOpcode::DclGlobalFlags:
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return this->emitDclGlobalFlags(ins);
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case DxbcOpcode::DclTemps:
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return this->emitDclTemps(ins);
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case DxbcOpcode::DclInput:
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case DxbcOpcode::DclInputSgv:
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case DxbcOpcode::DclInputSiv:
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case DxbcOpcode::DclInputPs:
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case DxbcOpcode::DclInputPsSgv:
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case DxbcOpcode::DclInputPsSiv:
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case DxbcOpcode::DclOutput:
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case DxbcOpcode::DclOutputSgv:
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case DxbcOpcode::DclOutputSiv:
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return this->emitDclInterfaceReg(ins);
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case DxbcOpcode::DclConstantBuffer:
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return this->emitDclConstantBuffer(ins);
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case DxbcOpcode::DclSampler:
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return this->emitDclSampler(ins);
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case DxbcOpcode::DclResource:
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return this->emitDclResource(ins);
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default:
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Logger::warn(
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str::format("DxbcCompiler: Unhandled opcode: ",
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ins.op));
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}
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}
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void DxbcCompiler::emitDclGlobalFlags(const DxbcShaderInstruction& ins) {
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// TODO implement properly
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}
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@ -962,13 +951,191 @@ namespace dxvk {
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emitRegisterStore(ins.dst[0], result);
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}
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void DxbcCompiler::emitControlFlowIf(const DxbcShaderInstruction& ins) {
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// Load the first component of the condition
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// operand and perform a zero test on it.
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const DxbcRegisterValue condition = emitRegisterLoad(
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ins.src[0], DxbcRegMask(true, false, false, false));
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void DxbcCompiler::emitRet(const DxbcShaderInstruction& ins) {
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const DxbcRegisterValue zeroTest = emitRegisterZeroTest(
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condition, ins.controls.zeroTest);
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// Declare the 'if' block. We do not know if there
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// will be an 'else' block or not, so we'll assume
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// that there is one and leave it empty otherwise.
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DxbcCfgBlock block;
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block.type = DxbcCfgBlockType::If;
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block.b_if.labelIf = m_module.allocateId();
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block.b_if.labelElse = m_module.allocateId();
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block.b_if.labelEnd = m_module.allocateId();
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block.b_if.hadElse = false;
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m_controlFlowBlocks.push_back(block);
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m_module.opSelectionMerge(
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block.b_if.labelEnd,
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spv::SelectionControlMaskNone);
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m_module.opBranchConditional(
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zeroTest.id,
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block.b_if.labelIf,
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block.b_if.labelElse);
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m_module.opLabel(block.b_if.labelIf);
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}
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void DxbcCompiler::emitControlFlowElse(const DxbcShaderInstruction& ins) {
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if (m_controlFlowBlocks.size() == 0
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|| m_controlFlowBlocks.back().type != DxbcCfgBlockType::If
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|| m_controlFlowBlocks.back().b_if.hadElse)
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throw DxvkError("DxbcCompiler: 'Else' without 'If' found");
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// Set the 'Else' flag so that we do
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// not insert a dummy block on 'EndIf'
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DxbcCfgBlock& block = m_controlFlowBlocks.back();
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block.b_if.hadElse = true;
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// Close the 'If' block by branching to
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// the merge block we declared earlier
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m_module.opBranch(block.b_if.labelEnd);
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m_module.opLabel (block.b_if.labelElse);
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}
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void DxbcCompiler::emitControlFlowEndIf(const DxbcShaderInstruction& ins) {
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if (m_controlFlowBlocks.size() == 0
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|| m_controlFlowBlocks.back().type != DxbcCfgBlockType::If)
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throw DxvkError("DxbcCompiler: 'EndIf' without 'If' found");
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// Remove the block from the stack, it's closed
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const DxbcCfgBlock block = m_controlFlowBlocks.back();
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m_controlFlowBlocks.pop_back();
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// End the active 'if' or 'else' block
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m_module.opBranch(block.b_if.labelEnd);
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// If there was no 'else' block in this construct, we still
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// have to declare it because we used it as a branch target.
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if (!block.b_if.hadElse) {
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m_module.opLabel (block.b_if.labelElse);
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m_module.opBranch(block.b_if.labelEnd);
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}
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// Declare the merge block
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m_module.opLabel(block.b_if.labelEnd);
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}
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void DxbcCompiler::emitControlFlowLoop(const DxbcShaderInstruction& ins) {
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// Declare the 'loop' block
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DxbcCfgBlock block;
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block.type = DxbcCfgBlockType::Loop;
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block.b_loop.labelHeader = m_module.allocateId();
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block.b_loop.labelBegin = m_module.allocateId();
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block.b_loop.labelContinue = m_module.allocateId();
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block.b_loop.labelBreak = m_module.allocateId();
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m_controlFlowBlocks.push_back(block);
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m_module.opBranch(block.b_loop.labelHeader);
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m_module.opLabel (block.b_loop.labelHeader);
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m_module.opLoopMerge(
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block.b_loop.labelBreak,
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block.b_loop.labelContinue,
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spv::LoopControlMaskNone);
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m_module.opBranch(block.b_loop.labelBegin);
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m_module.opLabel (block.b_loop.labelBegin);
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}
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void DxbcCompiler::emitControlFlowEndLoop(const DxbcShaderInstruction& ins) {
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if (m_controlFlowBlocks.size() == 0
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|| m_controlFlowBlocks.back().type != DxbcCfgBlockType::Loop)
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throw DxvkError("DxbcCompiler: 'EndLoop' without 'Loop' found");
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// Remove the block from the stack, it's closed
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const DxbcCfgBlock block = m_controlFlowBlocks.back();
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m_controlFlowBlocks.pop_back();
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// Declare the continue block
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m_module.opBranch(block.b_loop.labelContinue);
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m_module.opLabel (block.b_loop.labelContinue);
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// Declare the merge block
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m_module.opBranch(block.b_loop.labelHeader);
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m_module.opLabel (block.b_loop.labelBreak);
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}
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void DxbcCompiler::emitControlFlowBreakc(const DxbcShaderInstruction& ins) {
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DxbcCfgBlock* loopBlock = cfgFindLoopBlock();
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if (loopBlock == nullptr)
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throw DxvkError("DxbcCompiler: 'Breakc' outside 'Loop' found");
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// Perform zero test on the first component of the condition
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const DxbcRegisterValue condition = emitRegisterLoad(
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ins.src[0], DxbcRegMask(true, false, false, false));
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const DxbcRegisterValue zeroTest = emitRegisterZeroTest(
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condition, ins.controls.zeroTest);
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// We basically have to wrap this into an 'if' block
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const uint32_t breakBlock = m_module.allocateId();
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const uint32_t mergeBlock = m_module.allocateId();
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m_module.opSelectionMerge(mergeBlock,
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spv::SelectionControlMaskNone);
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m_module.opBranchConditional(
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zeroTest.id, breakBlock, mergeBlock);
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m_module.opLabel(breakBlock);
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m_module.opBranch(loopBlock->b_loop.labelBreak);
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m_module.opLabel(mergeBlock);
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}
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void DxbcCompiler::emitControlFlowRet(const DxbcShaderInstruction& ins) {
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// TODO implement properly
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m_module.opReturn();
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m_module.functionEnd();
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}
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void DxbcCompiler::emitControlFlow(const DxbcShaderInstruction& ins) {
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switch (ins.op) {
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case DxbcOpcode::If:
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return this->emitControlFlowIf(ins);
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case DxbcOpcode::Else:
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return this->emitControlFlowElse(ins);
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case DxbcOpcode::EndIf:
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return this->emitControlFlowEndIf(ins);
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case DxbcOpcode::Loop:
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return this->emitControlFlowLoop(ins);
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case DxbcOpcode::EndLoop:
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return this->emitControlFlowEndLoop(ins);
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case DxbcOpcode::Breakc:
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return this->emitControlFlowBreakc(ins);
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case DxbcOpcode::Ret:
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return this->emitControlFlowRet(ins);
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default:
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Logger::warn(str::format(
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"DxbcCompiler: Unhandled instruction: ",
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ins.op));
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}
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}
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DxbcRegisterValue DxbcCompiler::emitRegisterBitcast(
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DxbcRegisterValue srcValue,
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@ -1131,6 +1298,23 @@ namespace dxvk {
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}
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DxbcRegisterValue DxbcCompiler::emitRegisterZeroTest(
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DxbcRegisterValue value,
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DxbcZeroTest test) {
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DxbcRegisterValue result;
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result.type.ctype = DxbcScalarType::Bool;
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result.type.ccount = 1;
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const uint32_t zeroId = m_module.constu32(0u);
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const uint32_t typeId = getVectorTypeId(result.type);
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result.id = test == DxbcZeroTest::TestZ
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? m_module.opIEqual (typeId, value.id, zeroId)
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: m_module.opINotEqual(typeId, value.id, zeroId);
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return result;
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}
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DxbcRegisterValue DxbcCompiler::emitSrcOperandModifiers(
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DxbcRegisterValue value,
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DxbcRegModifiers modifiers) {
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@ -1433,7 +1617,7 @@ namespace dxvk {
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default:
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Logger::warn(str::format(
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"dxbc: Unhandled vertex sv output: ",
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"DxbcCompiler: Unhandled vertex sv output: ",
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svMapping.sv));
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}
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}
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@ -1538,14 +1722,26 @@ namespace dxvk {
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}
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DxbcCfgBlock* DxbcCompiler::cfgFindLoopBlock() {
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for (auto cur = m_controlFlowBlocks.rbegin();
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cur != m_controlFlowBlocks.rend(); cur++) {
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if (cur->type == DxbcCfgBlockType::Loop)
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return &(*cur);
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}
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return nullptr;
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}
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uint32_t DxbcCompiler::getScalarTypeId(DxbcScalarType type) {
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switch (type) {
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case DxbcScalarType::Uint32: return m_module.defIntType(32, 0);
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case DxbcScalarType::Uint64: return m_module.defIntType(64, 0);
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case DxbcScalarType::Sint32: return m_module.defIntType(32, 1);
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case DxbcScalarType::Sint64: return m_module.defIntType(64, 1);
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case DxbcScalarType::Uint32: return m_module.defIntType(32, 0);
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case DxbcScalarType::Uint64: return m_module.defIntType(64, 0);
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case DxbcScalarType::Sint32: return m_module.defIntType(32, 1);
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case DxbcScalarType::Sint64: return m_module.defIntType(64, 1);
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case DxbcScalarType::Float32: return m_module.defFloatType(32);
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case DxbcScalarType::Float64: return m_module.defFloatType(64);
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case DxbcScalarType::Bool: return m_module.defBoolType();
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}
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throw DxvkError("DxbcCompiler: Invalid scalar type");
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@ -82,6 +82,37 @@ namespace dxvk {
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};
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enum class DxbcCfgBlockType : uint32_t {
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If, Loop,
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};
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struct DxbcCfgBlockIf {
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uint32_t labelIf;
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uint32_t labelElse;
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uint32_t labelEnd;
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bool hadElse;
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};
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struct DxbcCfgBlockLoop {
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uint32_t labelHeader;
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uint32_t labelBegin;
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uint32_t labelContinue;
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uint32_t labelBreak;
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};
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struct DxbcCfgBlock {
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DxbcCfgBlockType type;
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union {
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DxbcCfgBlockIf b_if;
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DxbcCfgBlockLoop b_loop;
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};
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};
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/**
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* \brief DXBC to SPIR-V shader compiler
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*
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@ -149,6 +180,11 @@ namespace dxvk {
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std::array<DxbcSampler, 16> m_samplers;
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std::array<DxbcShaderResource, 128> m_textures;
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///////////////////////////////////////////////
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// Control flow information. Stores labels for
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// currently active if-else blocks and loops.
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std::vector<DxbcCfgBlock> m_controlFlowBlocks;
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///////////////////////////////////////////////////////////
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// Array of input values. Since v# registers are indexable
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// in DXBC, we need to copy them into an array first.
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@ -173,14 +209,17 @@ namespace dxvk {
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/////////////////////////////////////////////////////
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// Shader interface and metadata declaration methods
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void emitDcl(
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const DxbcShaderInstruction& ins);
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void emitDclGlobalFlags(
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const DxbcShaderInstruction& ins);
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const DxbcShaderInstruction& ins);
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void emitDclTemps(
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const DxbcShaderInstruction& ins);
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const DxbcShaderInstruction& ins);
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void emitDclInterfaceReg(
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const DxbcShaderInstruction& ins);
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const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitDclInput(
|
||||
uint32_t regIdx,
|
||||
|
|
@ -228,9 +267,31 @@ namespace dxvk {
|
|||
void emitSample(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitRet(
|
||||
/////////////////////////////////////
|
||||
// Control flow instruction handlers
|
||||
void emitControlFlowIf(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowElse(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowEndIf(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowLoop(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowEndLoop(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowBreakc(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlowRet(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
void emitControlFlow(
|
||||
const DxbcShaderInstruction& ins);
|
||||
|
||||
/////////////////////////////////////////
|
||||
// Generic register manipulation methods
|
||||
|
|
@ -262,6 +323,10 @@ namespace dxvk {
|
|||
DxbcRegisterValue emitRegisterNegate(
|
||||
DxbcRegisterValue value);
|
||||
|
||||
DxbcRegisterValue emitRegisterZeroTest(
|
||||
DxbcRegisterValue value,
|
||||
DxbcZeroTest test);
|
||||
|
||||
DxbcRegisterValue emitSrcOperandModifiers(
|
||||
DxbcRegisterValue value,
|
||||
DxbcRegModifiers modifiers);
|
||||
|
|
@ -333,6 +398,10 @@ namespace dxvk {
|
|||
uint32_t emitNewVariable(
|
||||
const DxbcRegisterInfo& info);
|
||||
|
||||
/////////////////////////////////////
|
||||
// Control flow block search methods
|
||||
DxbcCfgBlock* cfgFindLoopBlock();
|
||||
|
||||
///////////////////////////
|
||||
// Type definition methods
|
||||
uint32_t getScalarTypeId(
|
||||
|
|
|
|||
|
|
@ -122,6 +122,7 @@ namespace dxvk {
|
|||
// operands. Doing this mostly automatically means that
|
||||
// the compiler can rely on the operands being valid.
|
||||
const DxbcInstFormat format = dxbcInstructionFormat(m_instruction.op);
|
||||
m_instruction.opClass = format.instructionClass;
|
||||
|
||||
for (uint32_t i = 0; i < format.operandCount; i++)
|
||||
this->decodeOperand(code, format.operands[i]);
|
||||
|
|
|
|||
|
|
@ -154,7 +154,7 @@ namespace dxvk {
|
|||
struct DxbcRegister {
|
||||
DxbcOperandType type;
|
||||
DxbcScalarType dataType;
|
||||
DxbcComponentCount componentCount;
|
||||
DxbcComponentCount componentCount;
|
||||
|
||||
uint32_t idxDim;
|
||||
DxbcRegIndex idx[DxbcMaxRegIndexDim];
|
||||
|
|
@ -225,6 +225,7 @@ namespace dxvk {
|
|||
*/
|
||||
struct DxbcShaderInstruction {
|
||||
DxbcOpcode op;
|
||||
DxbcInstClass opClass;
|
||||
DxbcOpModifiers modifiers;
|
||||
DxbcShaderOpcodeControls controls;
|
||||
DxbcShaderSampleControls sampleControls;
|
||||
|
|
|
|||
|
|
@ -12,19 +12,27 @@ namespace dxvk {
|
|||
/* And */
|
||||
{ },
|
||||
/* Break */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* Breakc */
|
||||
{ },
|
||||
{ 1, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* Call */
|
||||
{ },
|
||||
{ 1, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* Callc */
|
||||
{ },
|
||||
{ 2, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* Case */
|
||||
{ },
|
||||
/* Continue */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* Continuec */
|
||||
{ },
|
||||
{ 1, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* Cut */
|
||||
{ },
|
||||
/* Default */
|
||||
|
|
@ -60,15 +68,15 @@ namespace dxvk {
|
|||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float32 },
|
||||
} },
|
||||
/* Else */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* Emit */
|
||||
{ },
|
||||
/* EmitThenCut */
|
||||
{ },
|
||||
/* EndIf */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* EndLoop */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* EndSwitch */
|
||||
{ },
|
||||
/* Eq */
|
||||
|
|
@ -101,7 +109,9 @@ namespace dxvk {
|
|||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Sint32 },
|
||||
} },
|
||||
/* If */
|
||||
{ },
|
||||
{ 1, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* IEq */
|
||||
{ 3, DxbcInstClass::VectorCmp, {
|
||||
{ DxbcOperandKind::DstReg, DxbcScalarType::Sint32 },
|
||||
|
|
@ -175,7 +185,7 @@ namespace dxvk {
|
|||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Float32 },
|
||||
} },
|
||||
/* Loop */
|
||||
{ },
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* Lt */
|
||||
{ 3, DxbcInstClass::VectorCmp, {
|
||||
{ DxbcOperandKind::DstReg, DxbcScalarType::Uint32 },
|
||||
|
|
@ -238,7 +248,9 @@ namespace dxvk {
|
|||
/* Ret */
|
||||
{ 0, DxbcInstClass::ControlFlow },
|
||||
/* Retc */
|
||||
{ },
|
||||
{ 1, DxbcInstClass::ControlFlow, {
|
||||
{ DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 },
|
||||
} },
|
||||
/* RoundNe */
|
||||
{ },
|
||||
/* RoundNi */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ namespace dxvk {
|
|||
*/
|
||||
enum class DxbcInstClass {
|
||||
Declaration, ///< Interface or resource declaration
|
||||
ControlFlow, ///< Control flow instructions
|
||||
TextureSample, ///< Texture sampling instruction
|
||||
VectorAlu, ///< Component-wise vector instructions
|
||||
VectorCmov, ///< Component-wise conditional move
|
||||
|
|
@ -36,7 +37,6 @@ namespace dxvk {
|
|||
VectorDot, ///< Dot product instruction
|
||||
VectorImul, ///< Component-wise integer multiplication
|
||||
VectorSinCos, ///< Sine and Cosine instruction
|
||||
ControlFlow, ///< Control flow instructions
|
||||
Undefined, ///< Instruction code not defined
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -470,6 +470,7 @@ namespace dxvk {
|
|||
Sint64 = 3,
|
||||
Float32 = 4,
|
||||
Float64 = 5,
|
||||
Bool = 6,
|
||||
};
|
||||
|
||||
}
|
||||
|
|
@ -1267,6 +1267,44 @@ namespace dxvk {
|
|||
}
|
||||
|
||||
|
||||
void SpirvModule::opLoopMerge(
|
||||
uint32_t mergeBlock,
|
||||
uint32_t continueTarget,
|
||||
uint32_t loopControl) {
|
||||
m_code.putIns (spv::OpLoopMerge, 4);
|
||||
m_code.putWord(mergeBlock);
|
||||
m_code.putWord(continueTarget);
|
||||
m_code.putWord(loopControl);
|
||||
}
|
||||
|
||||
|
||||
void SpirvModule::opSelectionMerge(
|
||||
uint32_t mergeBlock,
|
||||
uint32_t selectionControl) {
|
||||
m_code.putIns (spv::OpSelectionMerge, 3);
|
||||
m_code.putWord(mergeBlock);
|
||||
m_code.putWord(selectionControl);
|
||||
}
|
||||
|
||||
|
||||
void SpirvModule::opBranch(
|
||||
uint32_t label) {
|
||||
m_code.putIns (spv::OpBranch, 2);
|
||||
m_code.putWord(label);
|
||||
}
|
||||
|
||||
|
||||
void SpirvModule::opBranchConditional(
|
||||
uint32_t condition,
|
||||
uint32_t trueLabel,
|
||||
uint32_t falseLabel) {
|
||||
m_code.putIns (spv::OpBranchConditional, 4);
|
||||
m_code.putWord(condition);
|
||||
m_code.putWord(trueLabel);
|
||||
m_code.putWord(falseLabel);
|
||||
}
|
||||
|
||||
|
||||
void SpirvModule::opReturn() {
|
||||
m_code.putIns (spv::OpReturn, 1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -434,6 +434,23 @@ namespace dxvk {
|
|||
uint32_t sampledImage,
|
||||
uint32_t coordinates);
|
||||
|
||||
void opLoopMerge(
|
||||
uint32_t mergeBlock,
|
||||
uint32_t continueTarget,
|
||||
uint32_t loopControl);
|
||||
|
||||
void opSelectionMerge(
|
||||
uint32_t mergeBlock,
|
||||
uint32_t selectionControl);
|
||||
|
||||
void opBranch(
|
||||
uint32_t label);
|
||||
|
||||
void opBranchConditional(
|
||||
uint32_t condition,
|
||||
uint32_t trueLabel,
|
||||
uint32_t falseLabel);
|
||||
|
||||
void opReturn();
|
||||
|
||||
private:
|
||||
|
|
|
|||
Loading…
Reference in New Issue