664 lines
19 KiB
C
664 lines
19 KiB
C
/*
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* Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#include <math.h>
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#include "util/half_float.h"
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#include "util/u_math.h"
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#include "ir3.h"
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#include "ir3_compiler.h"
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#include "ir3_shader.h"
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#define swap(a, b) \
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do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
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/*
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* Copy Propagate:
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*/
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struct ir3_cp_ctx {
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struct ir3 *shader;
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struct ir3_shader_variant *so;
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bool progress;
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};
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/* is it a type preserving mov, with ok flags?
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*
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* @instr: the mov to consider removing
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* @dst_instr: the instruction consuming the mov (instr)
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*
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* TODO maybe drop allow_flags since this is only false when dst is
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* NULL (ie. outputs)
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*/
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static bool is_eligible_mov(struct ir3_instruction *instr,
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struct ir3_instruction *dst_instr, bool allow_flags)
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{
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if (is_same_type_mov(instr)) {
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struct ir3_register *dst = instr->regs[0];
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struct ir3_register *src = instr->regs[1];
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struct ir3_instruction *src_instr = ssa(src);
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/* only if mov src is SSA (not const/immed): */
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if (!src_instr)
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return false;
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/* no indirect: */
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if (dst->flags & IR3_REG_RELATIV)
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return false;
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if (src->flags & IR3_REG_RELATIV)
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return false;
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if (src->flags & IR3_REG_ARRAY)
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return false;
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if (!allow_flags)
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if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG |
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IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT))
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return false;
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/* If src is coming from fanout/split (ie. one component of a
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* texture fetch, etc) and we have constraints on swizzle of
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* destination, then skip it.
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*
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* We could possibly do a bit better, and copy-propagation if
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* we can CP all components that are being fanned out.
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*/
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if (src_instr->opc == OPC_META_SPLIT) {
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if (!dst_instr)
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return false;
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if (dst_instr->opc == OPC_META_COLLECT)
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return false;
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if (dst_instr->cp.left || dst_instr->cp.right)
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return false;
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}
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return true;
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}
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return false;
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}
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/* propagate register flags from src to dst.. negates need special
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* handling to cancel each other out.
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*/
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static void combine_flags(unsigned *dstflags, struct ir3_instruction *src)
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{
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unsigned srcflags = src->regs[1]->flags;
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/* if what we are combining into already has (abs) flags,
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* we can drop (neg) from src:
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*/
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if (*dstflags & IR3_REG_FABS)
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srcflags &= ~IR3_REG_FNEG;
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if (*dstflags & IR3_REG_SABS)
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srcflags &= ~IR3_REG_SNEG;
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if (srcflags & IR3_REG_FABS)
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*dstflags |= IR3_REG_FABS;
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if (srcflags & IR3_REG_SABS)
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*dstflags |= IR3_REG_SABS;
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if (srcflags & IR3_REG_FNEG)
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*dstflags ^= IR3_REG_FNEG;
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if (srcflags & IR3_REG_SNEG)
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*dstflags ^= IR3_REG_SNEG;
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if (srcflags & IR3_REG_BNOT)
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*dstflags ^= IR3_REG_BNOT;
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*dstflags &= ~IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_SSA;
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*dstflags |= srcflags & IR3_REG_CONST;
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*dstflags |= srcflags & IR3_REG_IMMED;
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*dstflags |= srcflags & IR3_REG_RELATIV;
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*dstflags |= srcflags & IR3_REG_ARRAY;
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*dstflags |= srcflags & IR3_REG_HIGH;
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/* if src of the src is boolean we can drop the (abs) since we know
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* the source value is already a postitive integer. This cleans
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* up the absnegs that get inserted when converting between nir and
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* native boolean (see ir3_b2n/n2b)
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*/
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struct ir3_instruction *srcsrc = ssa(src->regs[1]);
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if (srcsrc && is_bool(srcsrc))
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*dstflags &= ~IR3_REG_SABS;
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}
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/* Tries lowering an immediate register argument to a const buffer access by
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* adding to the list of immediates to be pushed to the const buffer when
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* switching to this shader.
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*/
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static bool
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lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
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struct ir3_register *reg, unsigned new_flags)
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{
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if (!(new_flags & IR3_REG_IMMED))
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return false;
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new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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if (!ir3_valid_flags(instr, n, new_flags))
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return false;
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unsigned swiz, idx, i;
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reg = ir3_reg_clone(ctx->shader, reg);
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/* Half constant registers seems to handle only 32-bit values
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* within floating-point opcodes. So convert back to 32-bit values.
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*/
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bool f_opcode = (is_cat2_float(instr->opc) ||
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is_cat3_float(instr->opc)) ? true : false;
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if (f_opcode && (new_flags & IR3_REG_HALF))
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reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
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/* in some cases, there are restrictions on (abs)/(neg) plus const..
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* so just evaluate those and clear the flags:
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*/
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if (new_flags & IR3_REG_SABS) {
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reg->iim_val = abs(reg->iim_val);
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new_flags &= ~IR3_REG_SABS;
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}
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if (new_flags & IR3_REG_FABS) {
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reg->fim_val = fabs(reg->fim_val);
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new_flags &= ~IR3_REG_FABS;
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}
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if (new_flags & IR3_REG_SNEG) {
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reg->iim_val = -reg->iim_val;
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new_flags &= ~IR3_REG_SNEG;
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}
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if (new_flags & IR3_REG_FNEG) {
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reg->fim_val = -reg->fim_val;
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new_flags &= ~IR3_REG_FNEG;
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}
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/* Reallocate for 4 more elements whenever it's necessary */
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struct ir3_const_state *const_state = ir3_const_state(ctx->so);
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if (const_state->immediate_idx == const_state->immediates_size * 4) {
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const_state->immediates = rerzalloc(const_state,
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const_state->immediates,
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__typeof__(const_state->immediates[0]),
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const_state->immediates_size,
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const_state->immediates_size + 4);
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const_state->immediates_size += 4;
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for (int i = const_state->immediate_idx; i < const_state->immediates_size * 4; i++)
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const_state->immediates[i / 4].val[i % 4] = 0xd0d0d0d0;
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}
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for (i = 0; i < const_state->immediate_idx; i++) {
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swiz = i % 4;
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idx = i / 4;
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if (const_state->immediates[idx].val[swiz] == reg->uim_val) {
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break;
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}
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}
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if (i == const_state->immediate_idx) {
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/* Add on a new immediate to be pushed, if we have space left in the
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* constbuf.
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*/
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if (const_state->offsets.immediate + const_state->immediate_idx / 4 >=
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ir3_max_const(ctx->so))
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return false;
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swiz = i % 4;
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idx = i / 4;
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const_state->immediates[idx].val[swiz] = reg->uim_val;
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const_state->immediates_count = idx + 1;
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const_state->immediate_idx++;
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}
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reg->flags = new_flags;
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reg->num = i + (4 * const_state->offsets.immediate);
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instr->regs[n + 1] = reg;
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return true;
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}
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static void
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unuse(struct ir3_instruction *instr)
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{
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debug_assert(instr->use_count > 0);
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if (--instr->use_count == 0) {
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struct ir3_block *block = instr->block;
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instr->barrier_class = 0;
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instr->barrier_conflict = 0;
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/* we don't want to remove anything in keeps (which could
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* be things like array store's)
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*/
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for (unsigned i = 0; i < block->keeps_count; i++) {
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debug_assert(block->keeps[i] != instr);
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}
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}
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}
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/**
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* Handles the special case of the 2nd src (n == 1) to "normal" mad
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* instructions, which cannot reference a constant. See if it is
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* possible to swap the 1st and 2nd sources.
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*/
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static bool
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try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
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{
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if (!is_mad(instr->opc))
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return false;
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/* NOTE: pre-swap first two src's before valid_flags(),
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* which might try to dereference the n'th src:
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*/
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swap(instr->regs[0 + 1], instr->regs[1 + 1]);
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/* cat3 doesn't encode immediate, but we can lower immediate
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* to const if that helps:
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*/
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if (new_flags & IR3_REG_IMMED) {
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new_flags &= ~IR3_REG_IMMED;
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new_flags |= IR3_REG_CONST;
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}
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bool valid_swap =
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/* can we propagate mov if we move 2nd src to first? */
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ir3_valid_flags(instr, 0, new_flags) &&
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/* and does first src fit in second slot? */
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ir3_valid_flags(instr, 1, instr->regs[1 + 1]->flags);
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if (!valid_swap) {
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/* put things back the way they were: */
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swap(instr->regs[0 + 1], instr->regs[1 + 1]);
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} /* otherwise leave things swapped */
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return valid_swap;
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}
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/**
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* Handle cp for a given src register. This additionally handles
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* the cases of collapsing immedate/const (which replace the src
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* register with a non-ssa src) or collapsing mov's from relative
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* src (which needs to also fixup the address src reference by the
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* instruction).
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*/
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static bool
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reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
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struct ir3_register *reg, unsigned n)
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{
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struct ir3_instruction *src = ssa(reg);
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if (is_eligible_mov(src, instr, true)) {
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/* simple case, no immed/const/relativ, only mov's w/ ssa src: */
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struct ir3_register *src_reg = src->regs[1];
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unsigned new_flags = reg->flags;
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combine_flags(&new_flags, src);
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if (ir3_valid_flags(instr, n, new_flags)) {
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if (new_flags & IR3_REG_ARRAY) {
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debug_assert(!(reg->flags & IR3_REG_ARRAY));
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reg->array = src_reg->array;
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}
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reg->flags = new_flags;
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reg->instr = ssa(src_reg);
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instr->barrier_class |= src->barrier_class;
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instr->barrier_conflict |= src->barrier_conflict;
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unuse(src);
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reg->instr->use_count++;
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return true;
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}
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} else if ((is_same_type_mov(src) || is_const_mov(src)) &&
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/* cannot collapse const/immed/etc into meta instrs: */
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!is_meta(instr)) {
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/* immed/const/etc cases, which require some special handling: */
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struct ir3_register *src_reg = src->regs[1];
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unsigned new_flags = reg->flags;
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combine_flags(&new_flags, src);
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if (!ir3_valid_flags(instr, n, new_flags)) {
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/* See if lowering an immediate to const would help. */
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if (lower_immed(ctx, instr, n, src_reg, new_flags))
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return true;
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/* special case for "normal" mad instructions, we can
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* try swapping the first two args if that fits better.
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*
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* the "plain" MAD's (ie. the ones that don't shift first
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* src prior to multiply) can swap their first two srcs if
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* src[0] is !CONST and src[1] is CONST:
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*/
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if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
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return true;
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} else {
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return false;
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}
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}
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/* Here we handle the special case of mov from
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* CONST and/or RELATIV. These need to be handled
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* specially, because in the case of move from CONST
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* there is no src ir3_instruction so we need to
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* replace the ir3_register. And in the case of
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* RELATIV we need to handle the address register
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* dependency.
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*/
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if (src_reg->flags & IR3_REG_CONST) {
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/* an instruction cannot reference two different
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* address registers:
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*/
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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conflicts(instr->address, reg->instr->address))
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return false;
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/* This seems to be a hw bug, or something where the timings
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* just somehow don't work out. This restriction may only
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* apply if the first src is also CONST.
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*/
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if ((opc_cat(instr->opc) == 3) && (n == 2) &&
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(src_reg->flags & IR3_REG_RELATIV) &&
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(src_reg->array.offset == 0))
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return false;
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/* When narrowing constant from 32b to 16b, it seems
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* to work only for float. So we should do this only with
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* float opcodes.
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*/
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if (src->cat1.dst_type == TYPE_F16) {
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if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
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return false;
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if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
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return false;
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}
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src_reg = ir3_reg_clone(instr->block->shader, src_reg);
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src_reg->flags = new_flags;
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instr->regs[n+1] = src_reg;
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if (src_reg->flags & IR3_REG_RELATIV)
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ir3_instr_set_address(instr, reg->instr->address);
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return true;
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}
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if ((src_reg->flags & IR3_REG_RELATIV) &&
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!conflicts(instr->address, reg->instr->address)) {
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src_reg = ir3_reg_clone(instr->block->shader, src_reg);
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src_reg->flags = new_flags;
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instr->regs[n+1] = src_reg;
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ir3_instr_set_address(instr, reg->instr->address);
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return true;
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}
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/* NOTE: seems we can only do immed integers, so don't
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* need to care about float. But we do need to handle
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* abs/neg *before* checking that the immediate requires
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* few enough bits to encode:
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*
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* TODO: do we need to do something to avoid accidentally
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* catching a float immed?
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*/
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if (src_reg->flags & IR3_REG_IMMED) {
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int32_t iim_val = src_reg->iim_val;
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debug_assert((opc_cat(instr->opc) == 1) ||
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(opc_cat(instr->opc) == 6) ||
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ir3_cat2_int(instr->opc) ||
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(is_mad(instr->opc) && (n == 0)));
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if (new_flags & IR3_REG_SABS)
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iim_val = abs(iim_val);
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if (new_flags & IR3_REG_SNEG)
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iim_val = -iim_val;
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if (new_flags & IR3_REG_BNOT)
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iim_val = ~iim_val;
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/* other than category 1 (mov) we can only encode up to 10 bits: */
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if (ir3_valid_flags(instr, n, new_flags) &&
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((instr->opc == OPC_MOV) ||
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!((iim_val & ~0x3ff) && (-iim_val & ~0x3ff)))) {
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new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
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src_reg = ir3_reg_clone(instr->block->shader, src_reg);
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src_reg->flags = new_flags;
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src_reg->iim_val = iim_val;
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instr->regs[n+1] = src_reg;
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return true;
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} else if (lower_immed(ctx, instr, n, src_reg, new_flags)) {
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/* Fell back to loading the immediate as a const */
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return true;
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}
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}
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}
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return false;
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}
|
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|
|
/* Handle special case of eliminating output mov, and similar cases where
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* there isn't a normal "consuming" instruction. In this case we cannot
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* collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
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* be eliminated)
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*/
|
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static struct ir3_instruction *
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eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
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{
|
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if (is_eligible_mov(instr, NULL, false)) {
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struct ir3_register *reg = instr->regs[1];
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if (!(reg->flags & IR3_REG_ARRAY)) {
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struct ir3_instruction *src_instr = ssa(reg);
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debug_assert(src_instr);
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ctx->progress = true;
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return src_instr;
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}
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}
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return instr;
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|
}
|
|
|
|
/**
|
|
* Find instruction src's which are mov's that can be collapsed, replacing
|
|
* the mov dst with the mov src
|
|
*/
|
|
static void
|
|
instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
|
|
{
|
|
if (instr->regs_count == 0)
|
|
return;
|
|
|
|
if (ir3_instr_check_mark(instr))
|
|
return;
|
|
|
|
/* walk down the graph from each src: */
|
|
bool progress;
|
|
do {
|
|
progress = false;
|
|
foreach_src_n (reg, n, instr) {
|
|
struct ir3_instruction *src = ssa(reg);
|
|
|
|
if (!src)
|
|
continue;
|
|
|
|
instr_cp(ctx, src);
|
|
|
|
/* TODO non-indirect access we could figure out which register
|
|
* we actually want and allow cp..
|
|
*/
|
|
if (reg->flags & IR3_REG_ARRAY)
|
|
continue;
|
|
|
|
/* Don't CP absneg into meta instructions, that won't end well: */
|
|
if (is_meta(instr) && (src->opc != OPC_MOV))
|
|
continue;
|
|
|
|
progress |= reg_cp(ctx, instr, reg, n);
|
|
ctx->progress |= progress;
|
|
}
|
|
} while (progress);
|
|
|
|
if (instr->regs[0]->flags & IR3_REG_ARRAY) {
|
|
struct ir3_instruction *src = ssa(instr->regs[0]);
|
|
if (src)
|
|
instr_cp(ctx, src);
|
|
}
|
|
|
|
if (instr->address) {
|
|
instr_cp(ctx, instr->address);
|
|
ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address));
|
|
}
|
|
|
|
/* we can end up with extra cmps.s from frontend, which uses a
|
|
*
|
|
* cmps.s p0.x, cond, 0
|
|
*
|
|
* as a way to mov into the predicate register. But frequently 'cond'
|
|
* is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
|
|
* just re-write the instruction writing predicate register to get rid
|
|
* of the double cmps.
|
|
*/
|
|
if ((instr->opc == OPC_CMPS_S) &&
|
|
(instr->regs[0]->num == regid(REG_P0, 0)) &&
|
|
ssa(instr->regs[1]) &&
|
|
(instr->regs[2]->flags & IR3_REG_IMMED) &&
|
|
(instr->regs[2]->iim_val == 0) &&
|
|
(instr->cat2.condition == IR3_COND_NE)) {
|
|
struct ir3_instruction *cond = ssa(instr->regs[1]);
|
|
switch (cond->opc) {
|
|
case OPC_CMPS_S:
|
|
case OPC_CMPS_F:
|
|
case OPC_CMPS_U:
|
|
instr->opc = cond->opc;
|
|
instr->flags = cond->flags;
|
|
instr->cat2 = cond->cat2;
|
|
ir3_instr_set_address(instr, cond->address);
|
|
instr->regs[1] = cond->regs[1];
|
|
instr->regs[2] = cond->regs[2];
|
|
instr->barrier_class |= cond->barrier_class;
|
|
instr->barrier_conflict |= cond->barrier_conflict;
|
|
unuse(cond);
|
|
ctx->progress = true;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Handle converting a sam.s2en (taking samp/tex idx params via register)
|
|
* into a normal sam (encoding immediate samp/tex idx) if they are
|
|
* immediate. This saves some instructions and regs in the common case
|
|
* where we know samp/tex at compile time. This needs to be done in the
|
|
* frontend for bindless tex, though, so don't replicate it here.
|
|
*/
|
|
if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
|
|
!(instr->flags & IR3_INSTR_B) &&
|
|
!(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
|
|
/* The first src will be a collect, if both of it's
|
|
* two sources are mov from imm, then we can
|
|
*/
|
|
struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
|
|
|
|
debug_assert(samp_tex->opc == OPC_META_COLLECT);
|
|
|
|
struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
|
|
struct ir3_instruction *tex = ssa(samp_tex->regs[2]);
|
|
|
|
if ((samp->opc == OPC_MOV) &&
|
|
(samp->regs[1]->flags & IR3_REG_IMMED) &&
|
|
(tex->opc == OPC_MOV) &&
|
|
(tex->regs[1]->flags & IR3_REG_IMMED)) {
|
|
instr->flags &= ~IR3_INSTR_S2EN;
|
|
instr->cat5.samp = samp->regs[1]->iim_val;
|
|
instr->cat5.tex = tex->regs[1]->iim_val;
|
|
|
|
/* shuffle around the regs to remove the first src: */
|
|
instr->regs_count--;
|
|
for (unsigned i = 1; i < instr->regs_count; i++) {
|
|
instr->regs[i] = instr->regs[i + 1];
|
|
}
|
|
|
|
ctx->progress = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
bool
|
|
ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
|
|
{
|
|
struct ir3_cp_ctx ctx = {
|
|
.shader = ir,
|
|
.so = so,
|
|
};
|
|
|
|
/* This is a bit annoying, and probably wouldn't be necessary if we
|
|
* tracked a reverse link from producing instruction to consumer.
|
|
* But we need to know when we've eliminated the last consumer of
|
|
* a mov, so we need to do a pass to first count consumers of a
|
|
* mov.
|
|
*/
|
|
foreach_block (block, &ir->block_list) {
|
|
foreach_instr (instr, &block->instr_list) {
|
|
|
|
/* by the way, we don't account for false-dep's, so the CP
|
|
* pass should always happen before false-dep's are inserted
|
|
*/
|
|
debug_assert(instr->deps_count == 0);
|
|
|
|
foreach_ssa_src (src, instr) {
|
|
src->use_count++;
|
|
}
|
|
}
|
|
}
|
|
|
|
ir3_clear_mark(ir);
|
|
|
|
foreach_output_n (out, n, ir) {
|
|
instr_cp(&ctx, out);
|
|
ir->outputs[n] = eliminate_output_mov(&ctx, out);
|
|
}
|
|
|
|
foreach_block (block, &ir->block_list) {
|
|
if (block->condition) {
|
|
instr_cp(&ctx, block->condition);
|
|
block->condition = eliminate_output_mov(&ctx, block->condition);
|
|
}
|
|
|
|
for (unsigned i = 0; i < block->keeps_count; i++) {
|
|
instr_cp(&ctx, block->keeps[i]);
|
|
block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
|
|
}
|
|
}
|
|
|
|
return ctx.progress;
|
|
}
|