mesa/src/freedreno/fdl
Connor Abbott 8183a728a2 tu: Fix stencil border color with has_z24uint_s8uint
On a650+ we use the new Z24UINT_S8UINT format to sample the stencil
aspect of D24S8, which returns stencil in the second component and also
uses the second integer component for the border color. However Vulkan
mandates that the first component is used for the stencil border color.
There's no workaround we know of, so we have to fall back to the old
behavior where there is a workaround. If we know the format, we can
fixup the border color ourselves though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
..
fd5_layout.c freedreno/a5xx: Diff reduction in fd5_layout to fd6_layout. 2021-11-04 22:49:29 +00:00
fd5_layout_test.c freedreno/fdl: Re-indent 2021-04-17 15:38:56 +00:00
fd6_format_table.c freedreno/fdl: use XYZW swap for PIPE_FORMAT_X24S8_UINT 2022-06-17 18:39:47 +00:00
fd6_format_table.h freedreno/a6xx: Rewrite the format table format/swap helpers. 2021-10-05 20:09:17 +00:00
fd6_layout.c freedreno/a6xx: Fix a bunch of 3D texture layout to match blob behavior. 2021-11-15 22:25:08 +00:00
fd6_layout_test.c freedreno/a6xx: Fix a bunch of 3D texture layout to match blob behavior. 2021-11-15 22:25:08 +00:00
fd6_view.c tu: Fix stencil border color with has_z24uint_s8uint 2022-06-29 03:00:56 +00:00
fd_layout_test.c freedreno/cffdump: Handle the TILE_ALL flag in unit test generation. 2021-11-15 22:25:08 +00:00
fd_layout_test.h freedreno/cffdump: Handle the TILE_ALL flag in unit test generation. 2021-11-15 22:25:08 +00:00
freedreno_layout.c freedreno/fdl: Give the tiling mode a nice name in debug dumps. 2021-06-17 22:47:51 +00:00
freedreno_layout.h freedreno/a6xx: Use fdl format swizzle 2022-06-29 03:00:56 +00:00
meson.build freedreno/fdl: Add fdl6_view 2021-10-18 16:00:38 +00:00